Mixed In-Memory Computing Noise Reduction via Split Partial Sums
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Solution Overview
Problem
Analog in-memory computing (AIMC) systems suffer from a lower signal-to-noise ratio (SNR) compared to digital solutions, which can impact the performance and accuracy of deep neural networks (DNNs) due to process, voltage, and temperature variations.
Innovation Solution
Implementing a mixed analog/digital in-memory computing system with noise reduction techniques, including a cross-bar array, analog-to-digital conversion, and logic operation units that split digital multipliers into most and least significant portions, preloading analog cells with representative signals, and generating output signals to determine a digital resulting value with reduced noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If analog in-memory computing is used to overcome the memory wall and enable massive computational parallelism, then computational efficiency and power consumption are improved, but signal-to-noise ratio deteriorates due to process, voltage, and temperature variations
Solution Approach 1:
The patent divides the analog computation process into multiple segments by implementing a multi-stage architecture where the crossbar array performs initial matrix-vector multiplication, followed by sequential stages that progressively refine the result. Each stage processes partial results and combines them with additional input data, effectively segmenting the computation to reduce noise accumulation while maintaining computational efficiency
Solution Approach 2:
The patent introduces digital-to-analog converters (DACs) and analog-to-digital converters (ADCs) as intermediary components between the analog crossbar array and digital processing units. These converters serve as mediators that translate between analog and digital domains, allowing noise filtering and signal conditioning to occur at transition points, thereby improving the overall signal-to-noise ratio while preserving the benefits of analog computation
2Measurement precision
If digital multipliers are implemented in analog in-memory computing, then computational accuracy is improved, but noise propagation increases affecting subsequent calculations
Solution Approach 1:
The patent extracts the multiplication operation from the analog domain and implements it using digital multipliers in subsequent processing stages. By taking out the multiplication function from the noisy analog crossbar array and performing it in the clean digital domain, the system achieves accurate multiplication while avoiding the generation and propagation of multiplication-related noise in the analog domain
Solution Approach 2:
The patent performs preliminary data processing and conditioning in digital stages before feeding data back to the analog crossbar array. This preliminary action includes filtering, scaling, and preparation of input data to minimize the introduction of noise during analog computation, thereby reducing noise propagation while maintaining computational accuracy
Data Source
AI summary
A mixed analog/digital in-memory computing device implements matrix vector multiplication with reduced noise for use by a deep neural network (DNN). For each row of a cross-bar array a multiplier is split into at least a most significant (MS) portion and a least significant (LS) portion and preloaded into at least two cells on one row and at least two different columns of the cross-bar array. An input activation (IA) value is driven onto input conductors of each row and an analog-to-digital converter (ADC) converts output signals from the two columns as a truncated MS partial sum and a truncated LS partial sum. A gain is applied to the truncated MS partial sum and added to the truncated LS partial sum to form a resulting value for one node of the DNN.