Mixed Metal Gate CMOS Transistors for Work Function Tuning
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Solution Overview
Problem
Conventional semiconductor processing faces challenges in fabricating CMOS transistors with metal gates due to differing work function requirements for PMOS and NMOS transistors, leading to high gate resistance, gate tunneling currents, and boron penetration, which complicates the production of complex system-on-a-chip dies with multiple transistor types.
Innovation Solution
The use of two different metals with distinct work functions for PMOS and NMOS transistors, allowing for swapping of metals between device types on a single die to simplify masking steps and achieve optimal performance for various transistor types, thereby forming multiple CMOS devices with varying characteristics without the need for additional costly processing steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single metal gate is used for both PMOS and NMOS transistors, then manufacturing complexity is reduced, but device performance deteriorates due to inability to meet different work function requirements
Solution Approach 1:
The patent divides the gate metal structure into two distinct metal layers (first metal gate and second metal gate) that can be selectively applied to different transistor regions. This segmentation allows PMOS and NMOS transistors to have different work functions while maintaining a unified gate structure design, resolving the contradiction between manufacturing simplicity and device performance.
Solution Approach 2:
The patent implements local quality by applying different metal materials to different spatial locations on the chip. Specifically, a first metal with work function suitable for PMOS is applied to PMOS gate regions, while a second metal with work function suitable for NMOS is applied to NMOS gate regions. This local differentiation enables optimal performance for each transistor type without requiring completely separate processing flows.
2Reliability
If multiple gate metals are used for different transistor types, then device performance is improved, but manufacturing complexity increases due to additional masking steps
Solution Approach 1:
The patent merges the deposition processes for different gate metals into a single unified masking step. By designing the mask pattern to simultaneously define both PMOS and NMOS gate regions, the process achieves multi-metal gate fabrication without proportionally increasing the number of masking operations. This combining approach reduces manufacturing complexity while maintaining the performance benefits of differentiated gate metals.
Solution Approach 2:
The patent creates a universal gate structure that can accommodate multiple metal types through a single processing flow. The gate electrode design and masking strategy are made multi-functional, allowing the same basic process steps to produce different metal configurations for PMOS and NMOS transistors. This universality eliminates the need for separate processing lines for each transistor type.
3Ease of manufacture
If heavily doped polysilicon gates are used, then manufacturing simplicity is maintained, but device reliability deteriorates due to gate depletion and boron penetration
Solution Approach 1:
The patent replaces the heavily doped polysilicon gate material system with a metal gate material system. This substitution eliminates the fundamental issues of polysilicon gates including gate depletion effects and boron penetration into the channel. The metal gate provides better electrical characteristics and stability while maintaining compatibility with standard CMOS fabrication processes.
Solution Approach 2:
The patent changes the fundamental material parameter of the gate from polysilicon to metal, which fundamentally alters the electrical and physical properties. This parameter change eliminates gate depletion and boron penetration issues inherent to polysilicon, while the metal gate provides superior control over threshold voltage and reduced gate leakage currents.
Data Source
AI summary
A semiconductor structure includes a first PMOS transistor element having a gate region with a first gate metal associated with a PMOS work function and a first NMOS transistor element having a gate region with a second metal associated with a NMOS work function. The first PMOS transistor element and the first NMOS transistor element form a first CMOS device. The semiconductor structure also includes a second PMOS transistor that is formed in part by concurrent deposition with the first NMOS transistor element of the second metal associated with a NMOS work function to form a second CMOS device with different operating characteristics than the first CMOS device.