Interconnection Line Structure With Mixed Metals for Low Resistivity

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Solution Overview

Problem

The scaling down of metal-oxide-semiconductor field-effect transistors (MOS-FETs) in semiconductor devices leads to deterioration in operational properties, necessitating improved electric characteristics to maintain performance.

Innovation Solution

The semiconductor device incorporates a structure with distinct linewidths and metallic materials for lower interconnection lines, including a first metal pattern with a second metal pattern of different material and volume, optimized to reduce resistivity and prevent short circuits, along with a via structure that avoids contact with adjacent lines to prevent short circuits.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of moving object

If MOS-FETs are scaled down to meet increasing demand for smaller pattern size, then the pattern size is reduced, but the operational properties of the semiconductor device deteriorate

Engineering Contradiction:

Improvepattern sizeVSAvoidoperational properties

Core Design Contradiction:

Area of moving objectVSReliability

Solution Approach 1:

The patent applies different materials (first metal pattern and second metal pattern with different metallic materials) to different regions of the interconnection lines based on their local requirements. The first metal pattern is used in regions where resistivity reduction is critical, while the second metal pattern is used in other regions, creating local optimization of electrical properties to maintain operational performance despite scaling.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The interconnection lines are constructed using composite material structures with multiple metal patterns stacked or adjacent to each other. This composite approach allows the device to leverage the advantageous properties of different metallic materials (such as copper for low resistivity and cobalt for barrier properties) to maintain electrical performance at scaled dimensions.

Inventive Principle:

Principle #40Composite materials

2Quantity of substance

If the linewidth of interconnection lines is reduced to increase transistor density, then the transistor density increases, but the resistivity of interconnection lines increases

Engineering Contradiction:

Improvetransistor densityVSAvoidresistivity

Core Design Contradiction:

Quantity of substanceVSLoss of energy

Solution Approach 1:

The patent employs composite interconnection line structures with multiple metal patterns (first metal pattern and second metal pattern) to reduce resistivity. By combining different metallic materials with complementary properties, the structure achieves lower overall resistivity than single-material lines of the same dimensions, compensating for the increased resistivity effect caused by reduced linewidth.

Inventive Principle:

Principle #40Composite materials

Solution Approach 2:

Instead of relying solely on increasing linewidth to reduce resistivity, the patent transitions to a vertical dimension by stacking multiple metal patterns (first metal pattern and second metal pattern) in layers. This multi-layer configuration increases the effective conductive cross-section vertically, thereby reducing resistivity without increasing the horizontal linewidth.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

3Reliability

If via depth is increased to connect to lower interconnection lines, then the electrical connection is improved, but the risk of short circuits with adjacent lines increases

Engineering Contradiction:

Improveelectrical connectionVSAvoidshort circuit risk

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent introduces an intermediary insulating layer between the via structure and adjacent lower interconnection lines. This insulating layer acts as a mediator that provides electrical isolation, allowing the via to extend deeply for good electrical connection while preventing harmful short circuits with neighboring lines through dielectric barrier.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The insulating layer is positioned in advance around the via structure to provide protective cushioning against potential short circuits. This preventive measure is built into the structure before operation, cushioning against the harmful effect of electrical breakdown or manufacturing variations that could cause short circuits between the deep via and adjacent lines.

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

Data Source

PatentUS12199042B2Semiconductor device having interconnection lines with different linewidths and metal patterns

Publication Date: 2025.01.14 SAMSUNG ELECTRONICS CO LTD

AI summary

A semiconductor device includes transistors on a substrate, a first interlayered insulating layer on the transistors, first and second lower interconnection lines in an upper portion of the first interlayered insulating layer, and first and second vias on the first and second lower interconnection lines, respectively. Each of the first and second lower interconnection lines includes a first metal pattern. The first lower interconnection line further includes a second metal pattern, on the first metal pattern with a metallic material different from the first metal pattern. The second metal pattern is absent in the second lower interconnection line. The second via includes first and second portions, which are in contact with respective top surfaces of the first interlayered insulating layer and the second lower interconnection line, and the lowest level of a bottom surface of the second portion is lower than that of a bottom surface of the first via.