Mixed-Metal Interconnect Structures for Low-Resistance Scaling
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Solution Overview
Problem
The scaling down of semiconductor devices and interconnect structures leads to increased resistance and capacitance, along with structural damage to inter-metal dielectric structures, posing challenges in achieving low-power, high-performance integrated circuits.
Innovation Solution
Implementing interconnect structures with different metals and cross-sectional areas to reduce resistance and capacitance, where interconnect lines with cross-sectional areas less than 400 nm² use metals with shorter electron mean free paths and higher bulk resistivity, and those above 400 nm² use metals with longer electron mean free paths and lower bulk resistivity, while forming narrow lines before the IMD structures to prevent damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If interconnect structures are scaled down to increase storage capacity and processing speed, then device performance is improved, but resistance and capacitance increase
Solution Approach 1:
The patent applies different metal materials to different cross-sectional area ranges of interconnect lines. Specifically, copper is used for lines with cross-sectional area ≥400 nm², while cobalt, tungsten, or ruthenium are used for lines with cross-sectional area <400 nm². This local differentiation optimizes electrical resistance for each size regime, addressing the worsening resistance characteristic as devices are scaled down.
Solution Approach 2:
The patent changes material parameters (electron mean free path and bulk resistivity) based on the cross-sectional area parameter. By selecting metals with appropriate electron mean free paths relative to the interconnect line dimensions, the patent optimizes electrical resistance across different scaling regimes, transforming the resistance-worsening trend into a controlled parameter optimization.
2Quantity of substance
If interconnect structures are scaled down to increase storage capacity, then storage capacity is improved, but resistance-capacitance delay increases
Solution Approach 1:
The patent implements local quality differentiation by assigning specific metal materials to different cross-sectional area ranges. This enables optimization of both resistance and capacitance characteristics for different interconnect dimensions, thereby reducing overall RC delay while maintaining high storage capacity through continued device scaling.
Solution Approach 2:
The patent employs composite material strategies by combining multiple metal materials (copper, cobalt, tungsten, ruthenium) within the same interconnect structure, each selected for specific cross-sectional area ranges. This composite approach allows simultaneous optimization of electrical properties across different dimensional regimes, reducing RC delay while enabling continued scaling for increased storage capacity.
3Power
If interconnect structures are scaled down to increase processing performance, then processing performance is improved, but breakdown voltage decreases
Solution Approach 1:
The patent changes material parameters including electron mean free path and bulk resistivity based on cross-sectional area. By selecting materials with appropriate electrical and mechanical properties for each size regime, the patent maintains breakdown voltage strength while enabling continued scaling for improved processing performance.
4Reliability
If narrow interconnect lines are formed after IMD structures to maintain structural integrity, then structural integrity is preserved, but manufacturing complexity increases
Solution Approach 1:
The patent applies preliminary action by forming narrow interconnect lines before depositing the inter-metal dielectric structures. This sequence prevents structural damage to the IMD that would occur if narrow lines were formed afterward, while the subsequent IMD deposition naturally protects and stabilizes the pre-formed narrow lines, reducing overall manufacturing complexity.
Solution Approach 2:
The patent inverts the conventional manufacturing sequence by forming narrow interconnect lines before the IMD structures rather than after. This inversion prevents structural damage to both the narrow lines and IMD, simplifying the manufacturing process while maintaining structural integrity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces electrical resistance and capacitance, enhancing the performance and reliability of semiconductor devices by minimizing electron scattering and structural damage.
Implementation Method 1
interconnect lines with cross-sectional areas less than 400 nm² have metals with electron mean free path lengths shorter than that of metals of the interconnect lines with cross-sectional areas greater than about 400 nm²
Implementation Method 2
interconnect lines with cross-sectional areas greater than about 400 nm² can have metals with bulk resistivity greater than that of metals of the interconnect lines with cross-sectional areas less than about 400 nm²
Data Source
AI summary
An interconnect structure and a method of fabricating the interconnect structure are disclosed. The interconnect structure includes an inter-metal dielectric (IMD) structure disposed on a transistor, first and second conductive lines disposed in the IMD structure, and a third conductive line, disposed in the IMD structure. The first conductive line includes a top surface with a first width and a bottom surface with a second width greater than the first width. The third conductive line includes an upper surface with a third width and a lower surface with a fourth width smaller than the third width. Metals of the first and third conductive lines are different from each other.