Mixed-Mode AI Multipliers for Low-Power Edge Computation
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Solution Overview
Problem
The increasing demand for low-power, high-performance chips in AI and ML applications is hindered by the energy inefficiency of purely digital computation, particularly at the edge or sensor levels, where conventional analog multipliers are impractical due to noise and cross-talk issues, and there is a need for cost-effective, low-power solutions that can operate with moderate accuracy and lower speeds.
Innovation Solution
The development of mixed-mode and analog signal processing solutions using data converters that share reference networks, operate asynchronously, and utilize approximate computation methods, such as segmentation and programming of transfer functions to follow logarithmic or square functions, to reduce power consumption and chip area while maintaining moderate accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If purely digital computation is used for AI and ML applications, then processing speed and accuracy are improved, but power consumption increases excessively
Solution Approach 1:
The patent merges digital and analog computing domains into a hybrid architecture where digital circuits handle control and data preparation while analog multipliers perform computational operations. This combination leverages the precision of digital systems and the energy efficiency of analog systems, achieving low power consumption without sacrificing computation accuracy.
Solution Approach 2:
The patent replaces traditional digital computational mechanisms with analog signal processing mechanisms for multiplication operations. By using analog voltage or current signals to represent data and perform multiplication through physical circuit operations rather than sequential digital logic, the system achieves significant power reduction while maintaining computational precision.
2Use of energy by moving object
If conventional analog multipliers are used, then power consumption is reduced, but noise and cross-talk issues worsen performance
Solution Approach 1:
The patent introduces digital signal processing stages as intermediaries before and after the analog multiplication operation. Digital-to-analog converters prepare clean input signals, and analog-to-digital converters reconstruct the output, with digital logic handling control functions. This intermediary digital infrastructure filters out noise and cross-talk from the analog domain while preserving the power efficiency benefits.
Solution Approach 2:
The patent applies different quality requirements to different parts of the system: high precision digital logic for control and data preparation, and relaxed tolerance analog circuits for the multiplication operation itself. By localizing the high-precision requirements to only where necessary and accepting approximate computation in the analog domain, the system achieves good signal quality without the power cost of fully digital high-precision circuits.
3Measurement precision
If high precision digital computation is implemented, then computation accuracy is improved, but chip area increases
Solution Approach 1:
The patent implements approximate computation in the analog domain where full precision is not critical, reserving high-precision digital computation only for control logic and data preparation. By applying partial precision where sufficient and full precision only where necessary, the system achieves adequate computation accuracy with significantly reduced chip area compared to fully digital high-precision implementations.
4Productivity
If Moore's law scaling continues, then transistor density and speed are improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent substitutes physical transistor scaling with analog signal processing techniques that achieve computational functionality without requiring proportionally higher transistor densities. By performing multiplication operations in the analog domain using continuous signals rather than discrete transistor switching, the system achieves high productivity without the manufacturing complexity and cost associated with continued Moore's law scaling.
Data Source
AI summary
Multipliers are fundamental building blocks in signal processing, including in emerging applications such as machine learning (ML) and artificial intelligence (AI) that predominantly utilize digital-mode multipliers. Generally, digital multipliers can operate at high speed with high precision, and synchronously. As the precision and speed of digital multipliers increase, generally the dynamic power consumption and chip size of digital implementations increases substantially that makes solutions unsuitable for some ML and AI segments, including in portable, mobile, or near edge and near sensor applications. The present invention discloses embodiments of multipliers that arrange data-converters to perform the multiplication function, operating in mixed-mode (both digital and analog), and capable of low power consumptions and asynchronous operations, which makes them suitable for low power ML and AI applications.