Mixed-Mode Compiler Error Detection via Simulation Comparison
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Solution Overview
Problem
Reconfigurable processors face challenges in efficiently handling data dependencies, leading to runtime errors when processing mixed-mode programs, as compilers struggle to analyze and optimize data flows across different execution modes, such as Coarse-Grained Array (CGA) and Very Long Instruction Word (VLIW) modes.
Innovation Solution
An apparatus and method for detecting source code errors in mixed-mode programs, involving a simulator, low-level data extractor, comparison data generator, and error location detector, which simulate and compare low-level data from programs compiled in different modes to generate verification and reference mapping tables, identifying inconsistent records and determining error locations based on program counters and Functional Unit indices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a compiler processes programs in multiple execution modes (CGA and VLIW), then the processor can handle diverse tasks efficiently, but data dependency analysis becomes difficult and runtime errors increase
Solution Approach 1:
The patent segments the program processing into two distinct execution modes (CGA mode and VLIW mode) with separate compilation and simulation paths. Each mode is processed independently through its own compiler instance and simulation workflow, allowing the system to handle diverse task types while maintaining reliable data dependency analysis within each segmented processing stream.
Solution Approach 2:
The patent introduces an intermediary verification mechanism that compares simulation results from both CGA and VLIW mode compilations. This intermediary comparison process acts as a mediator to detect data dependency errors that may arise in either mode, thereby improving reliability without sacrificing the adaptability of multi-mode execution.
2Productivity
If the compiler optimizes for performance in reconfigurable hardware, then processing speed improves, but detection of source code errors becomes more difficult
Solution Approach 1:
The patent creates a copy of the source program and compiles it through two different pathways (CGA mode and VLIW mode). By maintaining these parallel copies and comparing their simulation outputs, the system can detect source code errors even when performance optimizations are applied, without significantly impacting the overall processing speed.
Solution Approach 2:
The patent performs preliminary simulation and verification before final execution. By simulating both CGA and VLIW mode compilations in advance and comparing their outputs, the system detects potential source code errors early in the development process, allowing corrections to be made before deployment to reconfigurable hardware.
3Power
If data is processed in binary form in CGA mode, then hardware optimization is achieved, but error detection capability is reduced
Solution Approach 1:
The patent implements a feedback mechanism where simulation results from both CGA and VLIW modes are compared to generate verification information. This feedback loop provides error detection capability by identifying inconsistencies between the two compilation modes, ensuring that valuable error information is not lost even when data is processed in optimized binary form in CGA mode.
Data Source
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AI summary
An apparatus for detecting a source code error location in a mixed-mode program is disclosed. The apparatus may include a compiler, a mapping table generator, a simulator, a comparison data generator and an error location detector. The apparatus extracts low-level data while simulating a verification program and while simulating a reference program. The low-level data is mapped to mapping tables for a verification program and a reference program, and by comparing the tables it is determined if there is an error in the mixed-mode program and if so, where.