Mixed-Mode Integrated Circuit Simulation With Unified HDL Netlists

Solution Overview

Problem

Conventional methods for simulating mixed-mode system-on-chip (SOC) designs, which include both analog and digital subsystems, suffer from low efficiency, high simulation times, and the need for multiple simulator licenses, with analog simulations requiring transistor-level HDL netlists and separate testbenches.

Innovation Solution

A novel simulation method using HDL-level netlists and HDL-based simulators, employing integral and differential-based equations with numerical integration or Euler's method for analog behavior modeling, allowing efficient and accurate simulation of mixed-mode systems with reduced license costs and simplified testbench setup.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If conventional co-simulation methods are used for mixed-mode SOC designs, then simulation accuracy is maintained, but simulation time increases significantly and multiple simulator licenses are required

Engineering Contradiction:

Improvesimulation accuracyVSAvoidsimulation time

Core Design Contradiction:

Measurement precisionVSLoss of time

Solution Approach 1:

The patent merges analog and digital simulation capabilities into a unified HDL-based simulation framework. By translating analog subsystems into HDL models that can be simulated using the same simulator as digital subsystems, the invention eliminates the need for separate analog simulators and reduces simulation time while maintaining accuracy through verified HDL analog models

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent creates a universal HDL-based simulation approach that can handle both analog and digital subsystems with a single simulator. The HDL analog models enable the same simulation tool to process mixed-mode designs uniformly, eliminating license requirements for multiple specialized simulators and streamlining the simulation workflow

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Measurement precision

If transistor-level HDL netlists are used for analog simulations, then simulation accuracy is improved, but device complexity and setup requirements increase

Engineering Contradiction:

Improveanalog simulation accuracyVSAvoidtestbench complexity

Core Design Contradiction:

Measurement precisionVSDevice complexity

Solution Approach 1:

The patent changes the abstraction level parameter for analog models from transistor-level to HDL-level representations. This parameter change maintains simulation accuracy by using verified HDL analog models while significantly reducing testbench complexity, as HDL models can be integrated using standard HDL interfaces rather than requiring complex transistor-level connections

Inventive Principle:

Principle #35Parameter changes

3Measurement precision

If separate analog and digital simulators are used, then simulation accuracy is maintained, but license costs and setup effort increase

Engineering Contradiction:

Improvesimulation accuracyVSAvoidlicense cost

Core Design Contradiction:

Measurement precisionVSEase of manufacture

Solution Approach 1:

The patent creates a universal HDL-based simulation approach that can handle both analog and digital subsystems with a single simulator. The HDL analog models enable the same simulation tool to process mixed-mode designs uniformly, eliminating license requirements for multiple specialized simulators and streamlining the simulation workflow

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent merges analog and digital simulation capabilities into a unified HDL-based simulation framework. By translating analog subsystems into HDL models that can be simulated using the same simulator as digital subsystems, the invention eliminates the need for separate analog simulators and reduces simulation time while maintaining accuracy through verified HDL analog models

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS20250307509A1Apparatus and method of optimizing an integrated circuit design

Publication Date: 2025.10.02 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

Method and apparatus for optimizing circuit design are disclosed. In one aspect, the method includes receiving a circuit design of an integrated circuit and identifying a first circuit design of a first subsystem of the IC and a second circuit design of a second subsystem of the IC. The first subsystem operates on a plurality of digital variable signals and the second subsystem operates on a plurality of analog variable signals. The method also includes synthesizing a first HDL netlist based on the first circuit design, synthesizing a second HDL netlist based on the second circuit design, and obtaining behaviors of the circuit design of the IC using a single HDL-based simulator with both the first HDL netlist and the second HDL netlist as inputs.