Integrated Circuit Design with Unified Mixed-Mode HDL Simulation
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Solution Overview
Problem
Conventional methods for simulating mixed-mode integrated circuits, which include both analog and digital subsystems, suffer from low efficiency, high simulation times, and the need for multiple simulator licenses, with analog simulations requiring transistor-level HDL netlists and separate testbenches, leading to inefficiencies and increased design time.
Innovation Solution
A novel simulation method using HDL-level netlists and HDL-based simulators, employing numerical integration and Euler's method for analog behavior modeling, allowing efficient and accurate simulation of mixed-mode systems with reduced license costs and minimal testbench setup.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional co-simulation methods are used for mixed-mode circuits, then both analog and digital subsystems can be simulated, but simulation time becomes excessively long and multiple simulator licenses are required
Solution Approach 1:
The patent merges the simulation of analog and digital subsystems into a unified HDL-based simulation environment. By translating analog circuit behavior into HDL models that execute within the digital simulator, the invention eliminates the need for separate analog simulation tools and their associated licenses, while dramatically reducing total simulation time through unified processing.
Solution Approach 2:
The patent substitutes traditional analog simulation mechanisms (transistor-level netlists, separate testbenches) with HDL-based digital simulation mechanisms. This replacement uses numerical integration and Euler's method implemented in HDL to model analog behavior, allowing the simulation to run entirely within the digital simulator infrastructure.
2Measurement precision
If transistor-level HDL netlists are used for analog simulation, then detailed analog behavior can be modeled, but device complexity and setup requirements increase
Solution Approach 1:
The patent creates a universal HDL modeling approach that can represent both digital logic and analog circuit behavior within the same language and simulation environment. This multi-functionality allows a single testbench structure to handle mixed-mode simulation without requiring separate analog testbenches, reducing overall system complexity while maintaining modeling precision.
Solution Approach 2:
The patent changes the fundamental parameters and methods used to describe analog behavior, transitioning from transistor-level netlists with complex electrical parameters to HDL models using numerical methods (numerical integration, Euler's method). This parameter transformation simplifies the representation of analog circuits while preserving their behavioral accuracy within the digital simulation framework.
3Productivity
If separate analog and digital simulators are used, then each subsystem can be optimized independently, but license costs and operational complexity increase
Solution Approach 1:
The patent combines the functionality of separate analog and digital simulators into a single HDL-based simulation platform. This merger eliminates the need to manage multiple simulator licenses and their associated costs, while streamlining operational procedures into a unified toolchain that handles both analog and digital subsystems through a single interface and licensing model.
Data Source
AI summary
Method and apparatus for optimizing circuit design are disclosed. In one aspect, the method includes receiving a circuit design of an integrated circuit and identifying a first circuit design of a first subsystem of the IC and a second circuit design of a second subsystem of the IC. The first subsystem operates on a plurality of digital variable signals and the second subsystem operates on a plurality of analog variable signals. The method also includes synthesizing a first HDL netlist based on the first circuit design, synthesizing a second HDL netlist based on the second circuit design, and obtaining behaviors of the circuit design of the IC using a single HDL-based simulator with both the first HDL netlist and the second HDL netlist as inputs.