Mixed-Mode Quarter-Square Multipliers for Low-Power ML Inference
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Solution Overview
Problem
The increasing demand for low-power, cost-effective solutions in integrated circuits for machine learning and artificial intelligence applications is hindered by the energy inefficiency of purely digital computation chips, particularly at the edge or in mobile devices, where moderate accuracy at lower speeds is sufficient, and conventional analog multipliers are impractical due to high power consumption and noise issues.
Innovation Solution
The development of mixed-mode data converter circuits that operate asynchronously, share reference networks, and utilize resistors or current sources to program non-linear transfer functions, enabling efficient multiplication with reduced power consumption and chip area, while integrating seamlessly with digital logic and CMOS manufacturing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If purely digital computation chips are used for machine learning applications, then processing speed and precision can be maintained, but power consumption becomes excessively high and cost increases
Solution Approach 1:
The patent merges digital and analog computing domains into a hybrid architecture where digital logic handles control and analog circuits perform multiplication operations. This combination allows the system to leverage the precision of digital computing while utilizing the energy efficiency of analog computing for specific mathematical operations, thereby reducing overall power consumption without sacrificing computation precision.
Solution Approach 2:
The patent introduces data converters (ADCs and DACs) as intermediary components that bridge the digital and analog domains. These converters enable seamless interaction between digital control logic and analog computation circuits, allowing precise digital-to-analog transformation and analog-to-digital conversion while maintaining system precision and enabling low-power analog operations.
2Use of energy by moving object
If conventional analog multipliers are used to reduce power consumption, then energy efficiency improves, but noise issues and high power consumption persist making them impractical
Solution Approach 1:
The patent applies local quality by implementing analog computation only in specific regions where it provides advantage (multiplication operations), while keeping other parts of the system digital. This localized approach allows the system to benefit from analog energy efficiency where needed while avoiding the noise and power consumption issues of fully analog designs through selective digital-analog hybrid architecture.
3Productivity
If digital circuits are shrunk to increase density and speed, then processing capability improves, but manufacturing complexity increases and Moore's law is approaching its limit
Solution Approach 1:
The patent substitutes mechanical/digital computation with analog computation for specific operations. By replacing digital multiplication circuits with analog circuitry that performs multiplication through physical laws (such as current-voltage relationships), the system achieves computation without relying on further miniaturization of digital transistors, thereby avoiding the manufacturing complexity associated with continuing Moore's law scaling.
4Area of stationary object
If analog circuits are used for multiplication operations, then chip area and power consumption are reduced, but manufacturing precision and noise immunity decrease
Solution Approach 1:
The patent uses data converters as intermediary components that ensure manufacturing precision is maintained despite using analog circuits. The ADCs and DACs provide precise transformation between digital and analog domains, compensating for analog circuit imperfections and ensuring that the final computation results meet required precision standards while benefiting from reduced chip area.
Data Source
AI summary
Multipliers are fundamental building blocks in signal processing, including in emerging applications such as machine learning (ML) and artificial intelligence (AI) that predominantly utilize digital-mode multipliers. Generally, digital multipliers can operate at high speed with high precision, and synchronously. As the precision and speed of digital multipliers increase, generally the dynamic power consumption and chip size of digital implementations increases substantially that makes solutions unsuitable for some ML and AI segments, including in portable, mobile, or near edge and near sensor applications. The present invention discloses embodiments of multipliers that arrange data-converters to perform the multiplication function, operating in mixed-mode (both digital and analog), and capable of low power consumptions and asynchronous operations, which makes them suitable for low power ML and AI applications.