Mixed-Mode PLL with Analog Spur Filtering for Fractional Noise
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Solution Overview
Problem
All-digital phase locked loops (ADPLLs) face challenges in reducing fractional spurs due to non-linearity from quantization errors and meta-stability of the time to digital converter (TDC) and digital controlled oscillator (DCO), which cannot be effectively filtered by digital low pass filters, leading to persistent noise in wireless applications.
Innovation Solution
A mixed-mode PLL is introduced, incorporating a digital sigma-delta modulator, a low pass filter, and a digital controlled oscillator with varactors dynamically coupled to the low pass filter, allowing for sigma-delta modulation of fractional bit signals to generate an analog control signal that improves the short-term frequency resolution of the DCO, and rearranging switches to eliminate non-monotonic frequency gain without using dynamic element matching (DEM).
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a digital low pass filter is used to filter fractional spur in an ADPLL, then the circuit design becomes simpler, but the fractional spur cannot be reduced to zero due to finite resolution quantization errors
Solution Approach 1:
An analog low pass filter is introduced as an intermediary component between the digital domain and the DCO. This analog filter effectively removes fractional spurs before they are converted to time domain by the DCO, solving the limitation of digital filtering while maintaining digital circuit simplicity.
Solution Approach 2:
The invention changes the filtering domain from digital to analog by introducing an analog low pass filter. This parameter change allows effective suppression of fractional spurs that cannot be eliminated by digital filtering alone, while the overall architecture remains predominantly digital.
2Measurement precision
If frequency dithering technique is used to improve DCO resolution, then long-term average frequency resolution improves, but short-term quantization error remains and fractional spur cannot be eliminated
Solution Approach 1:
The analog low pass filter is applied before the DCO converts the frequency control word to time domain. This preliminary filtering action removes the fractional spur components before they can be amplified by the DCO's quantization process, preventing rather than correcting the problem.
Solution Approach 2:
The analog low pass filter serves as a mediator between the digital frequency control and the DCO's time domain conversion. It processes the frequency control signal to remove harmful spectral components while preserving the desired frequency information.
3Measurement precision
If the DCO quantization error is reduced by using smaller MOS capacitor geometry, then the resolution of the digital loop filter improves, but the required capacitor size becomes smaller than what advanced process can provide
Solution Approach 1:
The invention replaces the need for ultra-fine capacitor geometry (mechanical/dimensional precision) with an analog low pass filter approach. Instead of relying on smaller capacitors that are beyond manufacturing capabilities, the solution uses signal processing in the analog domain to achieve the desired resolution improvement.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces fractional spurs by more than 9 dB, improving the phase noise floor and maintaining immunity to thermal and switching noise, while requiring minimal additional silicon area and cost.
Implementation Method 1
The low pass filter receives an output signal of the digital sigma-delta modulator and converts the output signal to an analog control signal
Implementation Method 2
The digital controlled oscillator comprises a varactor dynamically coupled to the low pass filter and receiving the analog control signal
Data Source
AI summary
A mixed-mode PLL is disclosed. The mixed-mode PLL comprises a digital sigma-delta modulator, a low pass filter, and a digital controlled oscillator. The digital sigma-delta modulator receives a fractional bit signal. The low pass filter is coupled to the digital sigma-delta modulator. The low pass filter receives an output signal of the digital sigma-delta modulator and converts the output signal to an analog control signal. The digital controlled oscillator comprises a varactor dynamically coupled to the low pass filter and receiving the analog control signal.