Mixed-Mode Serial Bus Interface for One-Wire and Two-Wire Communication
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Solution Overview
Problem
Current serial communication technologies face challenges in efficiently managing communication between devices configured for one-wire and two-wire communication, particularly in mobile communication devices with complex bus architectures, where increased functionality and stringent timing constraints demand improved GPIO and communication link throughput.
Innovation Solution
The method involves transmitting a sequence start condition over a serial bus to indicate whether clock pulses are provided concurrently with data, using pulse-width modulation and phase modulation to encode data, and embedding timing information in the data signal, allowing for efficient communication with both one-wire and two-wire slave devices on a shared bus.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple separate communication interfaces are used to support both one-wire and two-wire devices, then device functionality and communication versatility are improved, but the number of I/O pins and bus architecture complexity increase
Solution Approach 1:
The serial bus is designed to operate in multiple modes (first mode with separate clock and data lines, second mode with clock embedded in data line) allowing a single bus architecture to support both one-wire and two-wire communication protocols, eliminating the need for separate dedicated interfaces for each protocol type
Solution Approach 2:
The bus architecture dynamically switches between two operational modes: in the first mode, clock and data are transmitted on separate lines for two-wire devices; in the second mode, clock pulses are embedded within the data line for one-wire devices. This dynamic reconfiguration allows the same physical infrastructure to adapt to different communication requirements without adding permanent complexity
2Reliability
If traditional separate clock and data line architecture is used, then communication reliability for two-wire devices is maintained, but the number of physical pins and connection complexity increase
Solution Approach 1:
The invention merges the clock signal and data signal into a single data line by embedding clock pulses within the data transmissions. This combining of previously separate signals reduces the physical pin count from two dedicated lines to one shared line, while maintaining communication reliability through the use of sequence start conditions that indicate whether clock pulses are embedded
3Quantity of substance
If clock pulses are embedded in the data line, then the number of I/O pins is reduced, but timing synchronization and signal interpretation become more complex
Solution Approach 1:
Before actual data transmission begins, the system transmits a sequence start condition that预先 indicates whether clock pulses will be embedded in the upcoming data transmissions. This preliminary signaling allows receiving devices to prepare their timing synchronization mechanisms in advance, reducing the complexity of real-time signal interpretation
Solution Approach 2:
The sequence start condition acts as a feedback mechanism that informs slave devices about the upcoming transmission mode. This feedback allows devices to automatically adjust their timing and sampling strategies based on the indicated mode, simplifying the overall synchronization process despite the embedded clock architecture
4Quantity of substance
If a unified serial bus is used for both one-wire and two-wire communication, then I/O pin count is reduced, but communication protocol complexity increases
Solution Approach 1:
The communication protocol is segmented into distinct transmission modes, each with clearly defined characteristics. The sequence start condition divides the communication flow into identifiable segments, allowing devices to process each segment according to its specific requirements without needing to handle all possible variations continuously
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient data transmission over a single wire, reducing bus latency and supporting high-priority messages, while minimizing the number of physical input/output pins required, thus enhancing communication efficiency and reducing complexity in multi-radio, multi-application systems.
Implementation Method 1
The transmitter may be configured to transmit data over the bus as a sequence of pulses within symbol slots. In the second mode of operation a transmission period of a first symbol slot may be stretched to prevent the I2C-compatible devices from changing into an unpredictable state as a result of a transition from a first pulse to a second pulse.
Data Source
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AI summary
The described systems, apparatus and methods enable communication between devices that use a single-wire link and devices that use a multi-wire link. One method performed at a master device includes transmitting a sequence start condition over a data wire of a serial bus, the sequence start condition indicating whether clock pulses are to be provided in a clock signal on a clock wire of the serial bus concurrently with a transaction initiated by the sequence start condition, transmitting a first datagram over the serial bus when the sequence start condition indicates that the clock pulses are to be concurrently provided in the clock signal, and transmitting a second datagram over the serial bus when the sequence start condition indicates that no clock pulses are to be concurrently provided in the clock signal. The second datagram may be transmitted in a data signal with embedded timing information.