Mixed-Orientation Nanosheet Transistors for Density-Current Tradeoffs

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Solution Overview

Problem

Conventional multi-bridge channel (MBC) transistors with nanowire channel members are not suitable for applications requiring high packing density and low power consumption, as they experience a drop in drive current due to their low effective width.

Innovation Solution

A semiconductor device is designed with both vertical and horizontal nanosheet channel members in different areas, where vertical nanosheet channel members provide increased packing density and horizontal nanosheet channel members enhance drive current and speed, tailored for specific applications by adjusting channel orientations and doping configurations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If conventional MBC transistors with nanowire channel members are used, then device performance is adequate for general applications, but drive current drops due to low effective width in high-performance applications

Engineering Contradiction:
Improvedrive currentVSAvoideffective width
Core Design Contradiction:
PowerVSProductivity

Solution Approach 1:

The patent transitions from conventional planar nanowire channels to three-dimensional nanosheet channels stacked vertically. This dimensional change allows the channel to provide both high effective width (through multiple stacked sheets) and adequate control, resolving the contradiction between drive current and effective width limitations of conventional MBC transistors.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The channel is segmented into multiple thin nanosheet layers stacked vertically, with each layer contributing to the effective width. This segmentation allows the total effective width to be increased while maintaining manageable dimensions for each individual sheet, thereby improving drive current without excessive complexity.

Inventive Principle:
Principle #1Segmentation

2Productivity

If vertical nanosheet channel members are used, then packing density increases, but drive current and speed may be compromised

Engineering Contradiction:
Improvepacking densityVSAvoiddrive current
Core Design Contradiction:
ProductivityVSPower

Solution Approach 1:

The patent applies different channel orientations (vertical vs. horizontal nanosheets) to different device areas based on local requirements. Vertical nanosheets are used where packing density is critical, while horizontal nanosheets are used where drive current and speed are prioritized, allowing each region to have optimized local quality.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The device structure allows dynamic selection of channel orientation and configuration based on application requirements. The ability to switch between vertical and horizontal nanosheet configurations enables the system to adapt to different performance demands, whether prioritizing packing density or drive current.

Inventive Principle:
Principle #15Dynamics

3Power

If horizontal nanosheet channel members are used, then drive current and speed are enhanced, but packing density decreases

Engineering Contradiction:
Improvedrive currentVSAvoidpacking density
Core Design Contradiction:
PowerVSProductivity

Solution Approach 1:

The patent implements spatial variation in nanosheet orientation, using horizontal nanosheets in regions requiring high drive current and speed, while using vertical nanosheets in regions requiring high packing density. This local quality approach allows each area to be optimized for its specific function.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS11908942B2Transistors having nanostructures
Publication Date: 2024.02.20 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11908942B2 patent drawing
  • US11908942B2 patent drawing
  • US11908942B2 patent drawing

AI summary

A semiconductor device according to the present disclosure includes a first transistor and a second transistor. The first transistor includes a plurality of first channel members and a first gate structure wrapping around each of the plurality of first channel members. The second transistor includes a plurality of second channel members and a second gate structure disposed over the plurality of second channel members. Each of the plurality of first channel members has a first width and a first height smaller than the first width. Each of the plurality of second channel members has a second width and a second height greater than the second width.