Mixed-Pitch BEOL Wiring for Dense FET Interconnect Scaling
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Solution Overview
Problem
Existing semiconductor technologies face challenges in further reducing the size of field-effect transistors (FETs) beyond atomic level scaling, particularly in achieving efficient miniaturization and increasing structural features without compromising performance and cost.
Innovation Solution
Implementing mixed pitch levels for back-end-of-line (BEOL) wiring layers with different sets of wires having varying minimum pitches and cross-sectional areas, allowing for the formation of interconnect wiring levels with both local and global connections, thereby reducing stack height and simplifying manufacturing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If uniform pitch levels are used for all wires in back-end-of-line wiring layers, then manufacturing processes are simplified, but the ability to optimize performance for different wire functions (local vs global connections) is compromised
Solution Approach 1:
The patent divides the interconnect wiring layer into multiple pitch levels, segmenting wires based on their functional requirements. Local interconnect wires use a first pitch level optimized for dense device connections, while global interconnect wires use a second pitch level optimized for longer-distance signaling. This segmentation allows each wire type to be optimized independently without compromising overall manufacturing feasibility.
Solution Approach 2:
Different regions of the interconnect wiring layer are assigned different pitch characteristics based on local functional requirements. The first pitch level is applied to regions requiring high-density local connections, while the second pitch level is applied to regions requiring global connectivity. This local quality approach enables performance optimization tailored to specific wiring functions while maintaining a unified manufacturing process.
2Length of moving object
If atomic level scaling is continued for FETs, then device size is reduced, but further miniaturization beyond atomic level becomes challenging
Solution Approach 1:
The patent addresses the limitation of continued atomic-level scaling by introducing pitch level differentiation as an additional design dimension. Instead of solely reducing FET dimensions, the invention optimizes the interconnect architecture by creating multiple pitch levels that accommodate different wiring functions. This dimensional approach to interconnect design enables continued device miniaturization while maintaining reliability through optimized wiring structures that adapt to scaled device dimensions.
Data Source
AI summary
A semiconductor structure includes at least one interconnect wiring level between a first device layer and a second device layer, wherein the at least one interconnect wiring level includes a first set of wires that are spaced apart from each other at a first minimum pitch, and a second set of wires that are spaced apart from each other at a second minimum pitch that is different than the first minimum pitch. The first set of wires comprises a first cross-sectional area and the second set of wires comprises a second cross-sectional area that is different than the first cross-sectional area.