Mixed-Polarity Transistor Stack Biasing for Common-Node Stability
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Solution Overview
Problem
In radio frequency (RF) amplifiers with stacked transistors of different polarities, maintaining voltage compliance across transistors of varying I-V characteristics and PVT variations can lead to malfunction or damage due to shifts in voltage at common nodes, especially during mode transitions between standby and active operations.
Innovation Solution
A circuit arrangement with N-type and P-type current mirrors in a closed loop feedback system adjusts gate biasing voltages at the input transistors of each stack to maintain a stable voltage at the common node, using error voltage generated from sensing the common node voltage, ensuring safe operation across different modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If gate biasing voltages are adjusted to control bias current through mixed polarity transistor stacks, then mode operation control is achieved, but voltage compliance of transistors may be violated due to different I-V characteristics and PVT variations
Solution Approach 1:
The patent implements a feedback mechanism by sensing the voltage at the common node between N-type and P-type transistor stacks and using this sensed voltage to dynamically adjust the gate biasing voltages. The feedback loop compares the sensed common node voltage with reference voltages and adjusts the biasing accordingly to maintain voltage compliance across all transistors during mode transitions between standby and active operations.
2Ease of operation
If separate biasing is applied to N-type and P-type transistor stacks, then individual current control is achieved, but voltage shifts at common nodes occur due to mismatched I-V characteristics
Solution Approach 1:
The patent applies counterbalancing by using complementary N-type and P-type current mirrors that generate equal and opposite biasing adjustments. When one stack's bias needs adjustment, the other stack's bias is adjusted in the opposite direction, counterbalancing the voltage shifts at the common node and maintaining stability despite separate current control.
3Reliability
If stacked transistors with different polarities are used to achieve push-pull topology, then linearity and noise figure performance are improved, but biasing complexity increases due to different PVT characteristics
Solution Approach 1:
The patent employs a universal biasing approach where a single control circuit generates biasing voltages for both N-type and P-type transistor stacks simultaneously. The biasing circuit performs multiple functions: it controls bias current, maintains voltage compliance, compensates for PVT variations, and stabilizes common node voltage, thereby managing the complexity of mixed polarity stacking through a unified control mechanism.
Data Source
AI summary
Various methods and circuital arrangements for biasing gates of stacked transistor amplifier that includes two series connected transistor stacks of different polarities are presented, where the amplifier is configured to operate according to different modes of operation. Such circuital arrangements operate in a closed loop with a feedback error voltage that is based on a sensed voltage at a common node of the two series connected transistor stacks. According to one aspect, gate biasing voltages to input transistors of each of the two series connected stacks are adjusted by respective current mirrors that are controlled based on the feedback error voltage. According to another aspect, other gate biasing voltages are generated by maintaining a fixed gate biasing voltage between any two consecutive gate basing voltages.