Mixed Precision Fused Multiply-Add Operator Circuit
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Solution Overview
Problem
Conventional FMA operators are underutilized and complex when handling mixed precision operands, requiring significant format conversion and increased complexity to achieve high precision results.
Innovation Solution
A mixed precision FMA operator that aligns and adds mantissas of operands with different precision formats, using a p-bit multiplier and shift circuits to convert operands to a higher precision format, reducing the complexity and size of the operator while maintaining high precision results.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional FMA operators are used to handle mixed precision operands, then high precision results can be achieved, but the complexity and size of the operator increases significantly
Solution Approach 1:
The patent segments the FMA operator into separate precision handling paths: a first precision path for multiplication operands and a second precision path for the addend. This allows each path to be optimized for its specific precision requirements, avoiding the need to design the entire operator for the highest precision level, thus reducing overall complexity while maintaining high precision results.
Solution Approach 2:
The patent applies local quality by assigning different precision formats to different parts of the operator: lower precision (e.g., binary32) for multiplication operands where it suffices, and higher precision (e.g., binary64) for the addend and final result where it is needed. This localized precision allocation reduces the complexity of components handling lower precision data while maintaining high precision where required.
2Measurement precision
If format conversion is performed to achieve high precision results with mixed precision operands, then calculation accuracy is improved, but calculation time and latency increase
Solution Approach 1:
The patent performs preliminary alignment of the addend with the product result before the addition operation. By pre-calculating the alignment shift based on exponent differences and preparing the addend in the correct format in advance, the actual addition operation can proceed without time-consuming format conversions during the critical calculation path, thus reducing latency.
Solution Approach 2:
The patent introduces an intermediary alignment mechanism that acts as a mediator between different precision formats. The alignment circuit prepares intermediate representations of operands in a common format suitable for addition, enabling efficient mixing of precision formats without requiring full format conversion of all operands, thereby reducing calculation time.
3Adaptability or versatility
If conventional FMA operators are designed for highest precision, then all precision formats can be accommodated, but the operator size and power consumption increase
Solution Approach 1:
The patent implements dynamic precision handling where the operator adapts its internal precision levels based on the input operands. The alignment circuit dynamically determines the appropriate precision level and alignment amount based on the exponent values and precision formats of the inputs, allowing the operator to operate efficiently at lower precision when possible while maintaining compatibility with higher precision formats when needed, thus reducing average power consumption.
Solution Approach 2:
The patent changes the precision parameter of different operand paths according to their requirements. By allowing multiplication operands to be processed in lower precision (reducing the bit-width and associated power consumption of multiplication circuits) while maintaining higher precision for the addend path, the operator achieves format compatibility without the full power cost of highest-precision operation throughout the entire circuit.
Data Source
AI summary
A circuit for calculating the fused sum of an addend and product of two multiplication operands, the addend and multiplication operands being binary floating-point numbers represented in a standardized format as a mantissa and an exponent is provided. The multiplication operands are in a lower precision format than the addend, with q>2p, where p and q are the mantissa size of the multiplication operand and addend precision formats. The circuit includes a p-bit multiplier receiving the mantissas of the multiplication operands; a shift circuit aligning the mantissa of the addend with the product output by the multiplier based on the exponent values of the addend and multiplication operands; and an adder processing q-bit mantissas, receiving the aligned mantissa of the addend and the product, the input lines of the adder corresponding to the product being completed to the right by lines at 0 to form a q-bit mantissa.