Mixed Precision Instruction Processing for RISC-V Execution Efficiency
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Solution Overview
Problem
Current processor architectures, such as RISC-V, lack standard instructions for mixed precision operations, necessitating the unification of operands to the same precision, which reduces execution efficiency for mixed precision models.
Innovation Solution
An instruction processing apparatus and method that decodes mixed precision operation instructions, allowing arithmetic operations on registers with different precisions without unification, and includes extension instructions for RISC-V architecture to execute operations directly, enhancing efficiency and reducing storage requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If standard instructions of the same precision operation are used for processing mixed precision operations, then the processor can execute operations using existing instruction sets, but the execution efficiency of mixed precision models is reduced
Solution Approach 1:
The patent introduces mixed precision operation instructions that change the precision parameter of operands during operation. The instruction system now supports operations with different precision parameters (e.g., 8-bit integer and 16-bit half-precision floating-point) without requiring unification to the same precision, thereby improving execution efficiency while maintaining manageable instruction set complexity through systematic parameter variation.
2Quantity of substance
If operands are unified to the same precision before processing, then standard instructions can be used, but storage requirements and computation overhead increase
Solution Approach 1:
The patent applies local quality by allowing different precision levels for different operands within the same operation. Instead of uniformly converting all operands to the same precision, the system permits each operand to maintain its appropriate precision level (e.g., weights in 8-bit integer, activations in 16-bit half-precision), reducing storage requirements and computation overhead while keeping operations simple through dedicated mixed precision instructions.
Data Source
AI summary
The disclosed embodiments of the present disclosure provide a processing method of mixed precision operation and an instruction processing apparatus. The instruction processing apparatus includes: a register file comprising a plurality of registers; an execution unit; and a decoding unit configured to decode a mixed precision operation instruction and acquire decoding information, the decoding information indicating the execution unit to execute following operations: executing appointed arithmetic operation on a first register and a second register of the plurality of registers, and writing an operation result back to a third register of the plurality of registers, precisions of operands of the first register and the second register being different; wherein the execution unit is coupled with the register file and the decoding unit and is configured to execute an operation corresponding to the decoding information. Compared with an existing processor, the instruction processing apparatus does not need to unify mixed precision into the same precision for arithmetic operation, thus improving the processing efficiency of the mixed precision.