Mixed Radix DFT Circuit Using Time-Shared Hardware
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Solution Overview
Problem
Existing digital signal processing technologies face inefficiencies in performing discrete Fourier transforms for sample sizes that are not a power of two, particularly in wireless communication standards like 3GPP LTE, which require radix-3 processing stages that are resource-intensive and complex to implement.
Innovation Solution
A circuit and method for performing mixed-radix discrete Fourier transforms by subdividing data frames into sub-frames of size N/3, using a fast Fourier transform processor block and radix-2 butterfly circuits to perform radix-3 operations efficiently, reducing hardware requirements and transform time through time-shared hardware and iterative radix-2 summations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a full-parallel radix-3 combinational stage is implemented, then streaming throughput is achieved allowing processing of complex data samples per clock cycle, but hardware resource consumption increases significantly requiring at least three complex multipliers and six complex add/subtracts
Solution Approach 1:
The radix-3 combinational stage is segmented into multiple iterative stages, where a single complex multiplier and adder are reused across different time steps to perform the same function that would otherwise require multiple parallel units. This temporal segmentation allows the same hardware resources to serve multiple operations sequentially.
Solution Approach 2:
The circuit employs periodic action by iterating through multiple processing stages in a sequential manner, where the same hardware resources are activated in different time periods to handle different aspects of the radix-3 computation, rather than operating continuously in parallel.
2Adaptability or versatility
If radix-3 processing is implemented within the FFT module itself, then integration is improved, but control logic and datapath complexity increase significantly
Solution Approach 1:
An intermediary iterative radix-3 processing stage is introduced between the FFT module and the output, which acts as a mediator to combine the FFT results with the necessary radix-3 operations. This intermediary stage handles the complexity of control logic and datapath modifications separately, allowing the FFT module itself to remain relatively simple while still achieving integrated functionality.
3Adaptability or versatility
If radix-3 processing is implemented for non-power-of-two sample sizes, then support for required bandwidths is achieved, but resource sensitivity becomes a constraint compared to power-of-two FFT implementations
Solution Approach 1:
The non-power-of-two sample size processing is segmented into an FFT portion (handling the power-of-two component) and a radix-3 iterative portion (handling the remaining factor), allowing each segment to be optimized independently for resource efficiency while supporting the required bandwidths.
Solution Approach 2:
The radix-3 processing for non-power-of-two sample sizes is implemented through periodic iterative stages that reuse the same hardware resources multiple times, reducing the overall resource footprint compared to a fully parallel implementation, while still achieving the required adaptability for different bandwidths.
Data Source
AI summary
An efficient circuit and method for performing radix-3 Discrete Fourier transform (DFT) of a 3*2M size data frame are provided. The data frame is split and fast Fourier transform (FFT) processed as three sub-frames. Radix-3 operations are performed on the FFT processed sub-frames over a number of stages with time shared hardware to compute the DFT of the data-frame. FFT operations are performed on the second and third sub-frames to produce respective sub-transforms. Concurrently with FFT processing of the first sub-frame, butterfly operations are performed on the sub-transforms of the second and third sub-frames. Through the use of time-shared hardware and arranging FFT operations to correspond with radix-3 operations at various stages of processing, the DFT is performed with existing FFT processors while reducing resource requirements and/or reducing DFT transform time over the full-parallel radix-3 implementation.