Mixed Radix FFT System Digit Reverse Addressing
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Solution Overview
Problem
Existing mixed-radix Fast Fourier Transform (FFT) systems face challenges in achieving high-throughput and efficient memory access due to complex data ordering and computational unit optimization, particularly for non-power of 2 FFT sizes, which increases computational complexity and memory overhead.
Innovation Solution
A system and method that utilize a single-port, single-bank memory with a digit reverse address generator, a register array acting as a cache, and a twiddle factor generator to perform in-place mixed-radix FFT computations, optimizing data access and reducing resource usage by generating digit reverse indices and using look-up tables for twiddle factor generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If mixed-radix FFT is used to support arbitrary FFT sizes, then adaptability is improved, but computational complexity increases
Solution Approach 1:
The FFT computation is segmented into multiple stages with different radices (e.g., radix-2, radix-4, radix-8). Each stage processes a portion of the data with a specific radix, allowing the system to handle arbitrary FFT sizes by combining different radix operations rather than using a single complex algorithm for all sizes.
Solution Approach 2:
The system dynamically changes the radix parameter across different computation stages. By varying the radix value (2, 4, 8, etc.) at different stages, the algorithm optimizes computational efficiency for specific FFT sizes while maintaining support for arbitrary sizes through configurable radix selection.
2Productivity
If multiple memory banks are used to support high-throughput, then productivity is improved, but device complexity increases
Solution Approach 1:
Multiple memory banks are merged into a single unified memory structure with a single port. This consolidation reduces the complexity of managing multiple independent memory banks while maintaining high-throughput capability through optimized data access patterns and interleaved memory organization within the single bank.
Solution Approach 2:
The single-port memory bank is designed to perform multiple functions: storing input data, storing intermediate computation results, and storing output data. The memory structure is universally applicable to different FFT sizes and radix configurations, eliminating the need for separate memory banks for different data stages.
3Manufacturing precision
If digit-reversed ordering is implemented for in-place computation, then manufacturing precision is improved, but ease of operation worsens
Solution Approach 1:
The input data is pre-arranged in digit-reversed order before the FFT computation begins. This preliminary reordering enables in-place computation throughout the algorithm, as each butterfly operation accesses data elements that are already positioned correctly, eliminating the need for additional reordering operations during computation.
Solution Approach 2:
Instead of the conventional approach where data is stored in natural order and reordered during or after computation, the system inverts the approach by storing data in digit-reversed order from the beginning. This inversion simplifies the computation logic and enables true in-place operations, as the reversed indexing naturally aligns with the butterfly operation requirements.
Data Source
AI summary
A system for implementing a mixed radix fast fourier transformation is disclosed. The system includes a data source 202, a digit-reverse address generator 204, a data memory 206, a register array 208, a control unit 210, a butterfly extraction unit 212, a twiddle factor generator 214, and a computation unit 216. The data source 202 provides input data. The digit reverse address generator 204 processes the input data (i) to generate a digit reverse index and performs a digits reverse address calculation. The data memory 206 stores the input data. The register array 208 includes one or more registers that are configured to cache multiple data words. The control unit 210 includes of identifying butterfly operations and generate addresses for fetching/storing data. The butterfly extraction unit 212 extracts data samples. The twiddle factor generator 214 generates and outputs a twiddle factors based on the current radix and radix configuration. The computation unit 216 performs twiddle factor multiplications and the butterfly operations for current radix.