Mixed Radix FFT Processor In-Place Storage
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Solution Overview
Problem
Current FFT devices face inefficiencies due to high memory access requirements and the need for simultaneous data and twiddle coefficient retrieval during butterfly computations in FFT algorithms, particularly in orthogonal frequency division multiple access (OFDMA), DFT-spread OFDMA, and single carrier frequency division multiple access (SC-FDMA) systems.
Innovation Solution
A mixed radix FFT unit with in-place data sample storage is employed, utilizing a counter-based memory addressing method to ensure simultaneous access and storage of data and twiddle coefficients across multiple radix stages, allowing for efficient computation of DFTs and IDFTs in LTE networks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a fully parallel FFT circuit is implemented to increase processing speed, then computation speed is improved, but memory access complexity and latency increase due to simultaneous data and twiddle coefficient retrieval requirements
Solution Approach 1:
The patent segments the FFT computation into multiple stages, with each stage handling a specific set of butterfly operations. The memory system is divided into multiple banks that can be accessed independently and simultaneously. This segmentation allows the complex memory access pattern to be broken down into manageable, parallel access operations, reducing overall memory access complexity while maintaining high processing speed.
Solution Approach 2:
The patent introduces a new dimension of organization by arranging memory banks in a multi-dimensional structure rather than a simple linear array. Memory addresses are mapped to multiple banks using a banking function that considers multiple address bits simultaneously. This dimensional reorganization enables simultaneous access to multiple memory locations without conflict, resolving the complexity issue while preserving parallel processing capability.
2Measurement precision
If data is stored and accessed from memory for each butterfly computation, then computation accuracy is improved, but memory access time increases due to the large number of reads and writes required
Solution Approach 1:
The patent implements preliminary action by pre-organizing data and twiddle coefficients in memory banks before computation begins. The memory addressing system is pre-configured with banking functions that map computation indices to specific memory banks. This preliminary organization ensures that all required data is readily accessible when needed, eliminating delays associated with dynamic memory allocation and access during computation, thus reducing memory access time while maintaining accuracy.
Solution Approach 2:
The patent ensures continuity of useful action by overlapping memory access operations with computation operations across different stages. While one stage is computing, another stage is simultaneously loading data into memory banks. The pipeline architecture allows continuous data flow through the system, eliminating idle time between memory accesses and computations, thereby reducing overall memory access time without compromising computational accuracy.
3Quantity of substance
If in-place data sample storage is used to reduce memory requirements, then memory efficiency is improved, but address computation complexity increases for correct data retrieval
Solution Approach 1:
The patent implements a universal memory addressing system that serves multiple functions simultaneously. The same memory banks are used for both input data storage and output data storage throughout the computation process. The banking function and address computation logic are designed to work uniformly across all computation stages, handling both data and twiddle coefficient access with the same mechanism. This multi-functionality reduces the need for separate storage areas while keeping address computation manageable through standardized procedures.
Solution Approach 2:
The patent introduces an intermediary addressing layer that mediates between the computation logic and the physical memory structure. The banking function acts as an intermediary that translates computation indices into physical memory addresses, handling the complexity of in-place storage mapping. This intermediary layer abstracts the address computation complexity from the main computation logic, making the system easier to implement while maintaining efficient in-place storage utilization.
Data Source
AI summary
An N-point Fast Fourier Transform (FFT) using mixed radix stages with in-place data sample storage may be performed by decomposing N into a product of R sequential mixed radix stages of radix-r(i). N data samples are partitioned into at least B memory banks, where B is equal to a largest radix of the R radix stages. Each input data sample to each radix-r(i) butterfly comes from r(i) different memory banks and the output data samples are written to the same memory locations in the r(i) memory banks. Determining from which memory bank the input data samples and output data samples of the butterflies are stored is done based on the radix size and sequential position of the radix stage. Determining the address of the input data samples and the output data samples within each memory bank is based on the radix size and sequential position of the radix stage.