Mixed RC Extraction for Semiconductor Layout Regions
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Solution Overview
Problem
The challenge in semiconductor device design is to balance accuracy and speed in resistance and capacitance (RC) extraction, as accurate RC extraction is crucial for timing simulations but demands more computing resources, leading to slower processing, especially at advanced process nodes with complex 3D structures and densely packed devices.
Innovation Solution
A method is introduced to perform accurate RC extraction in areas where accuracy is preferred and less accurate extraction where speed is needed, combining different RC extraction tools and methodologies to achieve a fast and accurate mixed RC extraction suitable for full chip RC extraction at advanced nodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If accurate RC extraction methodology is used inside regions, then measurement precision is improved, but computing resources consumption increases and processing speed decreases
Solution Approach 1:
The patent divides the layout into multiple regions and applies different RC extraction methodologies to different regions. Specifically, a first (more accurate) RC extraction methodology is applied to a first region, while a second (less accurate but faster) RC extraction methodology is applied to a second region. This segmentation allows the system to achieve high accuracy where needed while maintaining overall processing efficiency.
Solution Approach 2:
The patent implements local quality by tailoring the RC extraction methodology to the specific requirements of each region. Regions requiring high precision (such as those with critical timing paths) receive the more accurate first methodology, while other regions use the faster second methodology. This localized approach optimizes the balance between accuracy and speed for each specific area of the layout.
2Manufacturing precision
If accurate RC extraction is performed for densely packed devices with complex 3D structures, then manufacturing precision is improved, but loss of time increases
Solution Approach 1:
The patent segments the layout into regions that can be processed with appropriate extraction methodologies. By dividing the complex full-chip layout into manageable regions, the system can apply computationally intensive accurate extraction methods to specific regions without requiring them to process the entire chip, thereby reducing total extraction time while maintaining precision where critical.
Solution Approach 2:
The patent changes the extraction parameters (accuracy level, methodology complexity) based on the specific characteristics of each region. For regions with complex 3D structures and dense packing where accuracy is paramount, the first methodology with higher precision parameters is used. For other regions, parameters are adjusted to favor faster processing, thus optimizing the time-accuracy tradeoff.
Data Source
AI summary
A semiconductor device design method performed by at least one processor comprises extracting, using a resistance and capacitance (RC) extraction tool, at least one first parasitic capacitance among electrical components inside one or more regions of a plurality of regions in a layout of a semiconductor device. The method also comprises extracting, using the RC extraction tool, at least one second parasitic capacitance among electrical components outside the regions of the plurality of regions. The method further comprises combining, using a netlist generator tool, the extracted first and second parasitic capacitances into a netlist representing the layout. The RC extraction tool is configured to extract the first parasitic capacitances inside at least one region of the plurality of regions using a methodology more accurate than that for extracting the second parasitic capacitances.