Hybrid Row Height Circuits for Gate Oxide Failure Tolerance

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Solution Overview

Problem

Integrated circuits face performance and reliability issues due to gate oxide breakdown, which affects processing speed and power consumption, and existing designs with single cell row height architectures result in large area overhead and poor performance.

Innovation Solution

The mixed cell row height architecture (MCRHA) is introduced, where shadow logic circuits are arranged in reduced height cell rows, allowing redundant transistors to maintain circuit operations in case of oxide failure, reducing area and pin cap overhead while maintaining performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If shadow logic circuits are arranged in normal height cell rows, then circuit operations can be maintained in case of oxide failure, but area overhead increases

Engineering Contradiction:

Improvecircuit operation continuityVSAvoidarea overhead

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent applies dimensionality change by arranging shadow logic circuits in reduced height cell rows instead of normal height rows. This vertical dimension optimization allows redundant transistors to be packed more densely in the vertical direction, maintaining reliability through oxide failure while reducing the overall area overhead of the integrated circuit cell rows

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Reliability

If shadow logic circuits are arranged in normal height cell rows, then circuit operations can be maintained in case of oxide failure, but pin cap overhead increases

Engineering Contradiction:

Improvecircuit operation continuityVSAvoidpin cap overhead

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the functionality of multiple cell rows by arranging shadow logic circuits in reduced height rows that can share routing resources and pin caps with adjacent rows. This consolidation reduces the total number of pin caps required while maintaining the ability to sustain circuit operations through oxide failure, thereby reducing device complexity

Inventive Principle:

Principle #5Merging (Combining)

3Device complexity

If single cell row height architecture is used, then device structure is simple, but area overhead is large

Engineering Contradiction:

Improvestructure simplicityVSAvoidarea overhead

Core Design Contradiction:

Device complexityVSArea of stationary object

Solution Approach 1:

The patent introduces dynamic row height configuration where cell rows can have different heights based on their functional requirements. Normal height rows accommodate standard logic circuits while reduced height rows accommodate shadow logic circuits, creating a dynamic, adaptable structure that optimizes area utilization without significantly increasing device complexity

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS12074069B2Semiconductor device and integrated circuit in hybrid row height structure

Publication Date: 2024.08.27 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A semiconductor device includes several first cell row an several second cell rows. The first cell rows extend in a first direction. Each of the first cell rows has a first row height. A first row of the first cell rows is configured for a first cell to be arranged. The second cell rows extend in the first direction. Each of the second cell rows has a second row height that is different from the first row height. At least one row of the second cell rows includes a portion for at least one second cell to be arranged. The portion has a third row height that is different from the first row height and the second row height.