Mixed Row Height IC Layout for Broken Fin Avoidance

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Solution Overview

Problem

Conventional electronic design automation (EDA) tools face challenges in designing circuits that balance performance, power consumption, and area without sacrificing circuit performance due to the use of a single cell height, leading to issues like 'broken fins' which reduce circuit performance.

Innovation Solution

The proposed solution involves designing integrated circuits using a hybrid row structure with mixed row heights, where cells with different numbers of active regions are arranged in rows with varying heights, allowing for flexible active region width and transition, thereby avoiding the issue of broken fins.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If a single cell height is used for the design, then alignment across cells from different cell libraries is avoided, but circuit performance is compromised due to broken fins

Engineering Contradiction:
Improvealignment across cellsVSAvoidcircuit performance
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The design is segmented into multiple cell rows, each with its own optimized cell height. This allows different segments (rows) to have different characteristics (cell heights optimized for performance vs. power) while maintaining overall alignment through the use of standard cell library conventions within each row.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different rows are assigned different cell heights based on their specific functional requirements. Performance-critical rows use taller cells with more fins for higher drive current, while power-critical rows use shorter cells with fewer fins for lower power consumption. Each row locally optimizes its cell height for its specific purpose.

Inventive Principle:
Principle #3Local quality

2Adaptability or versatility

If cells with different numbers of fins are disposed side-by-side to balance performance and power, then a balance-orientated circuit is achieved, but broken fins occur which lower circuit performance

Engineering Contradiction:
Improvebalance between performance and powerVSAvoidcircuit performance
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The solution moves from a two-dimensional planar arrangement where cells are placed side-by-side in a single row, to a three-dimensional arrangement with multiple rows stacked vertically. This allows cells with different fin counts to be arranged in different rows rather than adjacent positions, eliminating the broken fin issue while maintaining performance-power balance.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The circuit is divided into multiple cell rows, each containing cells with uniform fin counts optimized for their specific function. This segmentation prevents the interleaving of cells with different fin counts that causes broken fins, while still enabling overall circuit balance through selective row placement.

Inventive Principle:
Principle #1Segmentation

3Device complexity

If a single cell height is used, then the design process is simplified, but the circuit cannot achieve optimal performance, power, and area balance

Engineering Contradiction:
Improvedesign process simplicityVSAvoidperformance-power-area balance
Core Design Contradiction:
Device complexityVSAdaptability or versatility

Solution Approach 1:

The design methodology is extended to support multiple cell heights while maintaining compatibility with standard cell library workflows. Each row can independently use cells optimized for its specific requirements, allowing the design process to achieve both simplicity (through standardized row-based organization) and versatility (through multi-height optimization).

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS20250159998A1Integrated circuit with mixed row heights
Publication Date: 2025.05.15 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250159998A1 patent drawing
  • US20250159998A1 patent drawing
  • US20250159998A1 patent drawing

AI summary

An integrated circuit structure includes: an integrated circuit structure includes: a first plurality of cell rows extending in a first direction, and a second plurality of cell rows extending in the first direction. Each of the first plurality of cell rows has a first row height and comprises a plurality of first cells disposed therein. Each of the second plurality of cell rows has a second row height different from the first row height and comprises a plurality of second cells disposed therein. The plurality of first cells comprises a first plurality of active regions each of which continuously extends across the plurality of first cells in the first direction. The plurality of second cells comprises a second plurality of active regions each of which continuously extends across the plurality of second cells in the first direction. At least one active region of the first and second pluralities of active regions has a width varying along the first direction.