Mixed RTL and Behavioral Circuit Simulation for Efficient Debugging
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Solution Overview
Problem
Debugging complex electronic systems with a combination of software, programmable logic, and ASIC components is cumbersome due to a lack of understanding of system-level interactions and resource-intensive full RTL implementations, which are further complicated by supplemental RTL debug logic affecting observability.
Innovation Solution
Generate an overall simulation model with behavioral and RTL simulation models, replacing behavioral models of suspect components with RTL models using an RTL extractor tool, reducing computational and memory resources while maintaining system-level interactions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If full RTL implementation is used for debugging, then debugging coverage is improved, but resource consumption and complexity increase significantly
Solution Approach 1:
The patent segments the simulation model into behavioral models for most components and RTL models only for suspect components. This segmentation allows debugging coverage to be focused on specific areas while avoiding the complexity of full RTL simulation across the entire system.
Solution Approach 2:
The patent applies local quality by using RTL simulation models selectively only for suspect components where detailed debugging is needed, while using behavioral models for other components. This creates different simulation qualities in different parts of the system based on debugging requirements.
2Reliability
If supplemental RTL debug logic is added, then debugging capability is improved, but observability of nets is degraded
Solution Approach 1:
The patent creates a copy of the suspect component's RTL model for simulation purposes, separate from the actual hardware implementation. This copy allows debugging without adding physical debug logic to the hardware, thereby preserving the original net observability in the actual device.
3Productivity
If behavioral models are used for all components, then simulation speed is improved, but debugging detail for specific components is reduced
Solution Approach 1:
The patent makes the simulation model dynamic by allowing substitution of behavioral models with RTL models for suspect components. This dynamic adjustment enables the simulation to maintain high speed for general operation while providing detailed debugging capability when needed for specific components.
Data Source
AI summary
Methods and systems for simulating RTL models in combination with behavioral models involve generating an overall simulation model from a circuit design by a simulation tool of an EDA system. The overall simulation model includes respective behavioral simulation models of components of the circuit design. A register transfer level (RTL) simulation model of a particular component of the components of the circuit design is generated by an extractor tool of the EDA system. The respective behavioral simulation model of the particular component in the overall simulation model is replaced with the RTL simulation model, and a simulation that executes the overall simulation model and the RTL simulation model in place of the behavioral simulation model of the particular component is performed.