Mixed Semiconductor Encapsulation with Stacked MOSFETs and Capacitors

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Solution Overview

Problem

Current semiconductor packaging technologies are inefficient in encapsulating both high-side and low-side MOSFETs and bypass capacitors within a single package, leading to increased component count, space requirements, and parasitic inductance, which hampers the performance of power converters and DC-DC converters.

Innovation Solution

A semiconductor package structure that integrates multiple chips and capacitors, including high-side and low-side MOSFETs and a power converter control IC, within a single encapsulation, utilizing a lead frame with specific pin configurations and metallic connectors to establish electrical connections, thereby minimizing parasitic inductance and reducing package size.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If multiple MOSFETs and capacitors are packaged separately, then each component can be optimized independently, but the component count increases and space requirements increase

Engineering Contradiction:

ImproveIndependent component optimizationVSAvoidComponent count

Core Design Contradiction:

Ease of manufactureVSQuantity of substance

Solution Approach 1:

The patent combines multiple MOSFET chips and capacitor chips into a single semiconductor package with a unified lead frame structure. The lead frame integrates multiple die pads for different chips and multiple pins that serve dual functions (e.g., source pins connected to both low-side MOSFET source and capacitor negative terminal), thereby reducing component count while maintaining manufacturability

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The lead frame pins are designed with multi-functionality: certain pins serve as common connection points for multiple components. For example, the source electrode pin connects to both the low-side MOSFET source electrode and the capacitor negative terminal, eliminating the need for separate connection terminals and reducing overall component count

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Ease of manufacture

If multiple MOSFETs and capacitors are packaged separately, then assembly is simplified, but space requirements increase

Engineering Contradiction:

ImproveAssembly simplicityVSAvoidPackage space

Core Design Contradiction:

Ease of manufactureVSArea of stationary object

Solution Approach 1:

The patent employs a nested arrangement where multiple chip components (MOSFET chips and capacitor chips) are mounted on different levels and areas of the same lead frame. The chips are electrically connected through the lead frame's conductive traces and pins, creating a compact integrated structure that reduces overall package space while maintaining assembly simplicity

Inventive Principle:

Principle #7Nested doll (Nesting)

Solution Approach 2:

The lead frame utilizes three-dimensional space by arranging chips and connection paths in multiple layers and dimensions. Electrical connections are established through vertical and horizontal traces on the lead frame, allowing compact packaging of multiple components without increasing the planar footprint

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

3Ease of manufacture

If bypass capacitor is placed away from MOSFETs, then packaging is easier, but parasitic inductance increases

Engineering Contradiction:

ImprovePackaging easeVSAvoidParasitic inductance

Core Design Contradiction:

Ease of manufactureVSObject-affected harmful factors

Solution Approach 1:

The capacitor chip is packaged within the same semiconductor package as the MOSFET chips, with all components mounted on the integrated lead frame. This merging of components into a single package ensures close physical proximity between the bypass capacitor and MOSFETs, minimizing parasitic inductance while maintaining packaging efficiency

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The lead frame is designed with localized electrical connection paths that provide direct, short-distance connections between the capacitor terminals and the MOSFET terminals. The conductive traces are routed to minimize loop area and inductance in the critical current paths, ensuring low parasitic inductance despite the integrated packaging

Inventive Principle:

Principle #3Local quality

4Quantity of substance

If multiple chips are integrated into one package, then component count reduces and space decreases, but device complexity increases

Engineering Contradiction:

ImproveComponent countVSAvoidPackage structure complexity

Core Design Contradiction:

Quantity of substanceVSDevice complexity

Solution Approach 1:

The lead frame is segmented into multiple functional zones with dedicated die pads for different chip types (MOSFET chips, capacitor chips) and separate pin groups for different electrical connections. This segmentation allows independent placement and connection of each chip type while maintaining an integrated package structure, reducing complexity through modular organization

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS8933550B2Structure of mixed semiconductor encapsulation structure with multiple chips and capacitors

Publication Date: 2015.01.13 ALPHA & OMEGA SEMICONDUCTOR INC

AI summary

A semiconductor package for power converter application comprises a low-side MOSFET chip and a high-side MOSFET chip stacking one over the other. The semiconductor package may further enclose a capacitor whereas the capacitor may be a discrete component or an integrated component on chip level with the low-side MOSFET. The semiconductor package may further comprise a PIC chip to provide a complete power converter on semiconductor chip assembly package level.