Mixed Serial Concurrent Logic Simulation for HDL Verification
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Solution Overview
Problem
Current logic simulation methods either perform simulations serially, which is inefficient for complex designs, or concurrently, which may not fully utilize hardware capabilities, leading to suboptimal verification of hardware designs before physical implementation.
Innovation Solution
An integrated logic simulator that combines a serial simulation engine and a concurrent simulation engine, allowing for partitioning of design modules and synchronization of interface variables to achieve efficient simulation performance, using industry-standard or proprietary interfaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If serial simulation engine is used, then simulation accuracy and HDL execution model compliance are maintained, but simulation speed and productivity deteriorate
Solution Approach 1:
The design is partitioned into multiple modules that can be simulated concurrently. Each module is simulated by a separate simulation engine instance, allowing parallel execution while maintaining individual module accuracy. The partitioning enables the system to process multiple design portions simultaneously, improving overall simulation speed without sacrificing HDL execution model compliance within each partition.
Solution Approach 2:
Multiple serial simulation engines are merged into a coordinated concurrent simulation system. The engines work together with a master controller that manages synchronization, combining the reliability of serial execution with the productivity of parallel processing. This merging allows the system to maintain strict HDL execution model compliance while achieving faster simulation through concurrent operation.
2Productivity
If concurrent simulation engine is used, then simulation speed and productivity are improved, but hardware capability utilization and measurement precision deteriorate
Solution Approach 1:
A master controller acts as an intermediary between concurrent simulation engines and the HDL execution model requirements. This mediator coordinates the concurrent engines, ensuring they produce accurate results by managing synchronization points and interface variable updates. The intermediary enables high-speed concurrent simulation while maintaining verification accuracy through controlled coordination.
Solution Approach 2:
The simulation system dynamically adjusts the level of concurrency and synchronization based on design characteristics and verification requirements. For critical paths requiring high precision, the system can increase synchronization frequency or use serial execution. For less critical portions, it maintains aggressive concurrency. This dynamic adaptation allows the system to optimize between speed and precision based on actual verification needs.
3Productivity
If design is partitioned between serial and concurrent engines, then simulation performance is optimized, but device complexity and interface management difficulty increase
Solution Approach 1:
The simulation system uses a universal interface standard for communication between serial and concurrent engines. This multi-functional interface handles multiple tasks including data exchange, synchronization coordination, and status reporting through a single standardized mechanism. The universal interface simplifies the complexity of coordinating multiple engine types by providing a common language and protocol for all interactions.
4Reliability
If interface variables are synchronized between engines, then simulation accuracy is maintained, but communication overhead and time consumption increase
Solution Approach 1:
Interface variable synchronization occurs periodically at defined synchronization points rather than continuously. The master controller establishes rhythmical synchronization intervals based on design characteristics and verification requirements. This periodic approach maintains simulation accuracy by ensuring interface variables are updated at critical moments while minimizing communication overhead by avoiding unnecessary continuous synchronization.
Data Source
AI summary
A method of simulating a design described in HDL is provided. In this method, modules of the design can be partitioned into first modules for simulation by a serial simulation engine and second modules for simulation by a concurrent simulation engine. The first and second modules can be prioritized for simulation based on classes of events consistent with an execution model of the HDL. Simulations of the serial and concurrent simulation engines can be synchronized for each class of events. Synchronizing can include transferring updated interface variable values, which are shared by the second modules and at least a subset of the first modules, between the serial simulation engine and the concurrent simulation engine. This transferring can include translating representations of the updated interface variable values.