Mixed-Sign Multiplier Circuit for Low-Power Partial Product Generation
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Solution Overview
Problem
Existing binary multiplier circuits face challenges such as latency, high power consumption, significant silicon area usage, and limited scalability, particularly when handling mixed signedness inputs or different data types.
Innovation Solution
The implementation of a mixed sign binary multiplier circuit that efficiently handles inputs of any signedness (both signed, both unsigned, or one signed and one unsigned) by using a novel method that reduces the required area by 11.6% and power consumption by 28%, while improving performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If conventional binary multiplier circuits are used, then multiplication operations can be performed, but the circuits consume high power and occupy significant silicon area
Solution Approach 1:
The multiplier circuit is divided into multiple partial product generators, each handling specific bit combinations. This segmentation allows parallel computation of partial products, reducing overall power consumption while maintaining multiplication capability through distributed processing across multiple low-power units.
Solution Approach 2:
The circuit merges signed and unsigned multiplication operations into a unified architecture that handles both types simultaneously. By combining the functionality of separate signed and unsigned multipliers into a single mixed-sign multiplier, the design reduces redundant circuitry and lowers overall power consumption while preserving full operational capability.
2Area of stationary object
If conventional binary multiplier circuits are used, then multiplication operations can be performed, but the circuits occupy significant silicon area
Solution Approach 1:
The multiplier circuit is designed with universal functionality to handle both signed and unsigned multiplication operations, as well as various data types (integers, fixed-point, floating-point). This multi-functional design eliminates the need for separate dedicated circuits for each operation type, significantly reducing silicon area while maintaining comprehensive multiplication capability.
Solution Approach 2:
The circuit dynamically adjusts its operation based on input parameters (signedness indicators, data type specifications) to optimize resource usage. By changing operational parameters rather than requiring separate hardware for each mode, the design reduces the required silicon area while preserving full operational flexibility.
3Device complexity
If conventional binary multiplier circuits are used, then multiplication operations can be performed, but the circuits exhibit high complexity and limited scalability
Solution Approach 1:
The multiplier circuit employs dynamic control mechanisms that adapt its internal configuration based on input characteristics (signedness, data type). This dynamic reconfiguration allows the same hardware structure to efficiently handle diverse multiplication scenarios without requiring complex dedicated circuits for each case, thereby reducing overall complexity while enhancing adaptability.
Solution Approach 2:
The design introduces intermediary control logic that mediates between diverse input types and the core multiplication engine. This intermediary layer translates various input formats (signed, unsigned, different data types) into a unified internal representation, simplifying the core computation logic and reducing circuit complexity while maintaining high versatility.
4Productivity
If conventional binary multiplier circuits are used, then multiplication operations can be performed, but the circuits exhibit high power consumption
Solution Approach 1:
The multiplier circuit implements local quality optimization by activating only the necessary partial product generators based on input characteristics. Instead of continuously operating all computation units, the design selectively enables specific segments of the circuit, reducing power consumption while maintaining full multiplication capability when needed.
Data Source
AI summary
An implementation may include a method for performing a binary multiplication including receiving a first at an input interface of a digital multiplier circuit in the computing system, receiving a second operand at the input interface of the digital multiplier circuit, generating, by the digital multiplier circuit, partial products by performing a AND operation with each of the N bits of the first operand and each of the bits of the second operand, and generating first modified partial products by modifying, by the digital multiplier circuit, most significant bits of the partial products, generating second modified partial products by modifying, by the digital multiplier circuit, one of the first modified partial product, generating, by the digital multiplier circuit, a product by summing the second modified partial products, and outputting the product from an output interface of the digital multiplier circuit.