Mixed-Signal Logic Circuit Using Charge Injection to Cut Capacitor Area
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Solution Overview
Problem
Existing mixed-signal operational circuits face challenges in reducing area overhead and improving energy efficiency while maintaining working speed and precision, particularly in deep neural network computations.
Innovation Solution
A mixed-signal operational circuit design utilizing a logic operational circuit and a convolution operational circuit that employs a charge injection method with MOS transistors and capacitors, reducing the need for unit weight capacitor arrays and implementing logical and convolution operations efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If charge sharing among capacitors is used for computation, then neural network operation precision is ensured, but capacitor area overhead increases significantly
Solution Approach 1:
The patent merges the weight storage function and computation function into a single capacitor array. The same capacitor array that stores weights is used to perform the computation through charge sharing, eliminating the need for separate weight storage memory and reducing overall area overhead while maintaining computation precision
Solution Approach 2:
The capacitor array serves multiple functions: it acts as both the weight storage medium and the computation element. By making the capacitor array universal, the design eliminates dedicated weight memory components and reduces the total area required while preserving the precision of neural network operations
2Speed
If capacitor plates are charged or discharged by voltage equal to power supply voltage, then computation speed is maintained, but energy consumption of switched capacitor adder circuit increases
Solution Approach 1:
The patent changes the voltage parameter from full power supply voltage swings to smaller differential voltage changes. By using differential signaling and smaller voltage excursions, the energy consumption is reduced while computation speed is maintained through efficient charge redistribution among capacitors
3Measurement precision
If unit weight capacitor array with size equal to add computation data is constructed, then computation precision is ensured, but area overhead becomes large in complex add computations
Solution Approach 1:
The patent segments the computation process into multiple stages using sequential charge redistribution. Instead of requiring all weight capacitors to be simultaneously available, the computation is broken down into steps where charge is redistributed sequentially, allowing the use of a smaller capacitor array that still achieves the required computation precision
Solution Approach 2:
The patent introduces dynamic switching control to manage the capacitor array during computation. By dynamically controlling which capacitors are connected and how charge is redistributed at different time steps, the system achieves complex addition computations with reduced area overhead while maintaining precision through controlled charge sharing
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Significantly reduces capacitor area overhead and enhances energy efficiency while ensuring high computational speed and precision, particularly in neural network operations.
Implementation Method 1
the amount of charge stored on the capacitor array is used as the measurement of change in the physical state, the charging and discharging of the capacitor and the redistribution process of the charge among the capacitor arrays are controlled by the switch
Implementation Method 2
a first MOS transistor, a second MOS transistor, a third MOS transistor... The source of the first MOS transistor is connected to the drain of the second MOS transistor... The logic operational channel is used to control the connection state between the drain terminal of the first MOS transistor and the output terminal VO based on the level state of the input data
Data Source
AI summary
A mixed-signal operational circuit is provided. For the operational circuit part of the mixed-signal operational circuit, a first capacitor is used to determine the output terminal of the logic operational circuit, a second capacitor is used to provide a certain voltage, and a logic operational channel selects the charge channel from the second capacitor to the first capacitor based on the data signal of each input, so as to superimpose the voltage value at the output terminal. Time-division multiplexing is achieved through successive injection, thereby an analog voltage value related to the logical operation result is established at the output terminal.