Mixed-Signal Current-Summing Circuit for Edge AI Inference

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Solution Overview

Problem

Traditional digital circuitry for neural network models is large, energy-intensive, and causes latency issues when deployed in edge devices due to the need for significant memory and compute resources, making it inefficient for real-time inference and energy-efficient AI processing.

Innovation Solution

The implementation of a mixed-signal integrated circuit with a binary-weighted global reference signal source, local differential current circuits, and a common-mode control circuit that adjusts differential current signals to perform weighted sum computations efficiently, reducing the need for large digital memory and energy consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If traditional digital circuitry is used for neural network computations, then compute power and memory capacity are sufficient, but circuit area and energy consumption increase significantly

Engineering Contradiction:
Improvecompute powerVSAvoidenergy consumption
Core Design Contradiction:
PowerVSUse of energy by moving object

Solution Approach 1:

The patent replaces traditional digital circuitry with a mixed-signal system that uses analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) to perform computations. The core innovation is using a current-mode analog computing core with binary-weighted current sources to perform multiply-accumulate operations, substituting digital switching and memory access with analog current summation, thereby reducing energy consumption while maintaining computational capability

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent changes the computational parameter domain from digital voltage levels to analog current magnitudes. By representing weights as binary-weighted current sources and inputs as analog voltages, the system performs weighted sum computations through physical current summation rather than digital multiplication and addition, fundamentally changing how computations are executed to reduce energy consumption

Inventive Principle:
Principle #35Parameter changes

2Quantity of substance

If traditional digital circuitry with large memory is used, then weight storage capacity is sufficient, but circuit area increases

Engineering Contradiction:
Improveweight storage capacityVSAvoidcircuit area
Core Design Contradiction:
Quantity of substanceVSArea of stationary object

Solution Approach 1:

The patent replaces digital memory structures with analog current sources. Instead of storing weight values in digital memory cells and reading them during computation, the system uses binary-weighted current sources where the weight is encoded in the current magnitude. This substitution eliminates the need for large digital memory arrays, significantly reducing circuit area while maintaining weight storage capacity

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The binary-weighted current sources serve multiple functions: they act as weight storage, weight multiplication, and contribute to the weighted sum computation simultaneously. This multi-functionality eliminates the need for separate memory and computation units, reducing overall circuit area while maintaining the capability to store and process hundreds or thousands of weights

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Power

If remote computing systems are used for neural network inference, then compute resources are adequate, but latency increases due to network transmission

Engineering Contradiction:
Improvecompute resourcesVSAvoidlatency
Core Design Contradiction:
PowerVSLoss of time

Solution Approach 1:

The patent segments the neural network inference function from remote cloud systems and implements it locally in edge devices. By integrating the mixed-signal computing core directly into the edge device, the system eliminates network transmission delays for both input data upload and inference result download, achieving real-time processing while maintaining adequate compute resources through the energy-efficient analog computing architecture

Inventive Principle:
Principle #1Segmentation

4Loss of time

If edge devices implement AI processing locally, then latency is reduced, but energy consumption and circuit complexity increase with traditional digital approaches

Engineering Contradiction:
ImprovelatencyVSAvoidenergy consumption
Core Design Contradiction:
Loss of timeVSUse of energy by moving object

Solution Approach 1:

The patent enables local AI processing in edge devices by replacing energy-intensive digital computation with analog current-mode computing. The mixed-signal architecture performs neural network inferencer operations using analog-to-digital converters, binary-weighted current sources, and current summation, achieving real-time processing at the edge while consuming significantly less energy than traditional digital implementations would require in resource-constrained edge devices

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS10903844B2System and methods for mixed-signal computing
Publication Date: 2021.01.26 MYTHIC INC
  • US10903844B2 patent drawing
  • US10903844B2 patent drawing
  • US10903844B2 patent drawing

AI summary

A mixed-signal integrated circuit that includes: a global reference signal source; a first summation node and a second summation node; a plurality of distinct pairs of current generating circuits arranged along the first summation node and the second summation node; a first current generating circuit of each of the plurality of distinct pairs that is arranged on the first summation node and a second current generating circuit of each of the plurality of distinct pairs is arranged on the second summation node; a common-mode current circuit that is arranged in electrical communication with each of the first and second summation nodes; where a local DAC adjusts a differential current between the first second summation nodes based on reference signals from the global reference source; and a comparator or a finite state machine that generates a binary output value current values obtained from the first and second summation nodes.