Mixed-Signal Switching Circuit for Low-Distortion DAC Clocks
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Solution Overview
Problem
High-speed digital-to-analogue converters (DACs) face issues with third-order distortion due to parasitic capacitances and timing mismatches, which are exacerbated by miniaturization and reduced transistor sizes, leading to increased distortion and power consumption.
Innovation Solution
The proposed solution involves a switching circuitry where data-controlled switches are placed in series with clock-controlled switches, allowing clock signals to directly drive clock-controlled switches without passing through data-controlled switches, and using a four-phase clock signal to ensure consistent switching operations, reducing distortion and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor sizes are reduced to increase conversion frequency, then productivity is improved, but third-order distortion increases due to parasitic capacitances
Solution Approach 1:
The switching operation is divided into two separate functions: data-controlled switches determine the output state, while dedicated clock-controlled switches provide the switching action. This segmentation isolates the data path from the clock path, preventing distortion while maintaining high-speed operation with miniaturized transistors.
Solution Approach 2:
Dedicated clock-controlled switches act as intermediaries between the clock signal and the data-controlled switches. These intermediary switches directly receive clock signals without passing through data-controlled switches, eliminating the distortion that would otherwise be introduced by the data path elements.
2Device complexity
If clock signals pass through data-controlled switches to control output switches, then device complexity is reduced, but timing mismatches increase leading to distortion
Solution Approach 1:
The circuit is segmented into distinct data-controlled switches and clock-controlled switches with separate control paths. This segmentation creates dedicated clock signal paths that are independent of data variations, ensuring consistent timing and eliminating timing mismatches that would otherwise occur.
Solution Approach 2:
Different parts of the switching circuit have specialized functions: data-controlled switches respond to data signals, while clock-controlled switches respond exclusively to clock signals. This local specialization ensures that clock timing is not affected by data transitions, eliminating timing mismatches while maintaining overall circuit functionality.
3Area of stationary object
If miniaturization is increased to reduce device size, then area is reduced, but parasitic capacitances increase causing distortion
Solution Approach 1:
The harmful effect of parasitic capacitances is extracted and isolated to specific locations in the circuit. By placing dedicated clock-controlled switches directly in the clock path, the parasitic capacitances are confined to well-defined nodes that can be managed separately from the data path, reducing their impact on overall distortion.
Data Source
AI summary
A switching circuit, comprising: a main switch having a control terminal; and a clock-path portion connected to the control terminal of the main switch to apply a driving clock signal thereto so as to drive the main switch, wherein the circuit is configured to controllably apply a biasing voltage to the clock-path portion so as to bias a voltage level of the driving clock signal as applied to the control terminal of the main switch.