Mixed-Signal Switching Circuit for Low-Distortion DAC Timing
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Solution Overview
Problem
High-speed digital-to-analogue converters (DACs) face issues with third-order distortion due to parasitic capacitances and timing mismatches, which are exacerbated by miniaturization and reduced transistor sizes, leading to increased distortion and power consumption.
Innovation Solution
The proposed solution involves a modified differential switching circuit with four FETs per output node, operating in a repeating series of phases based on complementary clock signals, and a switch driver circuitry that uses time-interleaved data signals and mask signals to reduce the impact of data-dependent charge flow and timing variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If transistor sizes are reduced to increase integration density, then device miniaturization is achieved, but third-order distortion increases due to parasitic capacitances
Solution Approach 1:
The switching operation is divided into multiple phases (first phase, second phase, third phase, fourth phase) with different sets of switches active in each phase. This segmentation allows the circuit to maintain proper switching function while reducing the impact of parasitic capacitances associated with any single small transistor, thereby reducing third-order distortion despite miniaturization.
Solution Approach 2:
The circuit employs periodic phase cycling through complementary clock signals (CLK1, CLK2, CLK3, CLK4) that activate different switch groups in a repeating sequence. This periodic action distributes the switching stress across multiple larger-effective transistors over time, reducing the distortion impact of individual miniaturized transistors while maintaining high conversion frequency.
2Area of moving object
If transistor sizes are reduced to increase integration density, then device miniaturization is achieved, but power consumption increases
Solution Approach 1:
The total switching task is segmented across multiple phases with different switch groups active in each phase. This allows the use of larger effective transistor sizes in each phase compared to a single-phase design, reducing leakage current and dynamic power consumption despite the miniaturized overall device footprint.
Solution Approach 2:
Complementary clock signals periodically activate different switch groups, ensuring that at any given time only a subset of switches is conducting. This periodic action reduces simultaneous switching noise and dynamic power consumption while maintaining the required conversion frequency, offsetting the power increase from miniaturization.
3Productivity
If switching speed is increased to achieve higher conversion frequencies, then productivity is improved, but timing mismatches increase due to parasitic capacitances
Solution Approach 1:
Four complementary clock signals (CLK1, CLK2, CLK3, CLK4) generate periodic switching phases that are distributed across different switch groups. This periodic multi-phase action balances the timing requirements across multiple larger-effective transistors, reducing timing mismatches caused by parasitic capacitances while achieving higher conversion frequencies.
Solution Approach 2:
The complementary clock signals act as intermediaries that coordinate the switching of different transistor groups across multiple phases. This intermediary timing mechanism compensates for variations in transistor switching characteristics caused by miniaturization, reducing timing mismatches while enabling higher conversion frequencies.
Data Source
AI summary
Mixed-signal circuitry, comprising: a first switching-circuitry unit for use in an analogue-to-digital converter; and a second switching-circuitry unit for use in a digital-to-analogue converter, wherein: the first switching-circuitry unit is configured to sample an input analogue signal and output a plurality of samples based on a first plurality of clock signals; the second switching-circuitry unit is configured to generate an output analogue signal based on a plurality of data signals and a second plurality of clock signals; and the first and second pluralities of clock signals have the same specifications as one another.