Mixed Signal Equivalence Checking via Segmentation
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Solution Overview
Problem
Mixed signal design verification is challenging due to the complex nature of combining analog and digital designs, with existing methods being error-prone and inadequate in detecting discrepancies between reference and verification models, especially in analog mixed signal circuits.
Innovation Solution
A hybrid mixed signal equivalence checking system that partitions models into analog and digital sections, using analog assertions and difference functions to verify equivalence by simulating and comparing digitized output values at interface cut points, and generating Boolean functions to determine digital equivalence.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If SPICE simulations and visual inspections are used to verify analog mixed signal models, then verification can be performed, but the process becomes error-prone and inadequate in detecting bugs
Solution Approach 1:
The patent divides the mixed signal model into separate analog and digital sections, allowing each section to be verified independently using appropriate methods. The analog section is verified through formal equivalence checking while the digital section uses traditional verification methods, improving overall verification reliability and bug detection precision.
Solution Approach 2:
The patent replaces manual visual inspection with automated formal equivalence checking for the analog section. This substitution of mechanical/manual verification with automated mathematical verification significantly improves both reliability and precision in detecting discrepancies between reference and verification models.
2Productivity
If analog circuit design and verification automation is applied, then verification efficiency improves, but systematic methodologies remain more primitive than digital design methodologies
Solution Approach 1:
By segmenting the verification process into analog and digital portions, the patent applies automation selectively where it provides the most benefit. The analog section receives formal equivalence checking automation while the digital section uses established methodologies, improving efficiency without unnecessarily complicating the entire verification process.
Solution Approach 2:
The patent introduces an intermediary layer of formal equivalence checking that bridges the analog and digital verification processes. This intermediary mechanism allows automated verification of analog circuits while maintaining compatibility with existing digital verification methodologies, improving productivity without excessive complexity.
3Ease of manufacture
If mixed signal designs are verified using traditional methods, then existing tools can be used, but discrepancies between reference and verification models are difficult to detect
Solution Approach 1:
The patent segments the model verification into two distinct parts: analog section verification using formal equivalence checking and digital section verification using traditional methods. This segmentation enables the use of existing tools for digital verification while adding formal verification capability for analog circuits, thereby improving discrepancy detection without requiring complete tool replacement.
Solution Approach 2:
The patent substitutes manual visual inspection with automated formal equivalence checking for the analog section. This substitution maintains ease of manufacture by using automated processes while dramatically improving the ability to detect discrepancies between reference and verification models through systematic mathematical comparison.
Data Source
AI summary
An approach is provided in which a hybrid mixed signal equivalence checking system partitions a mixed signal reference model and a mixed signal model under verification into analog sections and digital sections. The hybrid mixed signal equivalence checking system simulates the analog sections from the two different models to determine analog equivalence. As such, the hybrid mixed signal equivalence checking system verifies digital equivalence between the digital reference section and the digital section model under verification in response to evaluating one or more difference functions that represent at least a portion of the first digital section and the second digital section. As a result, the hybrid mixed signal equivalence checking system verifies equivalence between the mixed signal reference model and the mixed signal model under verification based upon the verified analog equivalence and the verified digital equivalence.