Mixed-Signal IC Fabrication via Selective Digital Block Shrinking
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Solution Overview
Problem
The existing methods for fabricating integrated circuits with enlarged digital blocks result in geometric structure coincidence issues and difficulties in managing design rule checks and optical proximity corrections, especially as technology advances and etching becomes finer, leading to potential production errors.
Innovation Solution
A process where the analog and digital blocks are designed and produced separately with selective dimensional reductions, allowing for controlled optical proximity corrections and alignment of critical mask levels, enabling the production of integrated circuits with minimal alteration to the analog block and maintaining correct cavity formation using the same etching process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If homogeneous homothetic reduction is applied to the entire integrated circuit to reduce footprint, then the footprint is reduced, but the geometric structure coincidence is destroyed and manufacturing precision deteriorates
Solution Approach 1:
The integrated circuit is divided into separate processing streams: one for the analog block in native technology and another for the digital block in shrunken technology. This segmentation allows each block to be processed independently with appropriate dimensional handling, preventing the geometric structure coincidence problems that arise from homogeneous reduction of the entire circuit.
Solution Approach 2:
Different parts of the integrated circuit are treated differently: the analog block maintains native technology dimensions while the digital block undergoes shrunken technology reduction. This local differentiation allows footprint reduction in the digital portion without compromising the geometric precision requirements of the analog portion.
2Area of stationary object
If homogeneous homothetic reduction is applied to reduce footprint, then the footprint is reduced, but design rule checks and optical proximity corrections become increasingly difficult to manage
Solution Approach 1:
The design process is segmented into separate flows for analog and digital blocks. Mask data is generated separately for each block with appropriate dimensional corrections applied only where needed, rather than attempting to manage complex DRC and OPC corrections across a uniformly reduced design.
3Area of stationary object
If the analog block is enlarged to apply homogeneous reduction, then footprint is reduced, but the pairing of transistors changes from native technology configuration
Solution Approach 1:
The analog block is processed locally in native technology without dimensional changes, preserving the original transistor pairings and their electrical characteristics. Only the digital block undergoes dimensional reduction, allowing footprint reduction while maintaining the reliability-critical analog transistor configurations.
Data Source
AI summary
The integrated circuit comprises an analog block and a digital block in and/or on the same substrate. At least part of a first integrated-circuit portion (BA2) corresponding to the analog block is produced in a native technology and a second integrated-circuit portion (BN2) corresponding to said digital block, is produced in a shrunk technological version associated with said native technology.