Mixed-Signal Circuit Verification via Formal Properties and Segmentation
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Solution Overview
Problem
Current electronic design automation (EDA) tools are inefficient in verifying the integration of mixed-signal circuits, requiring excessive time for comprehensive verification, which increases the risk of approving incorrect designs for production.
Innovation Solution
The method involves generating an executable specification file with integration abstractions, automatically creating a formal properties file, modeling analog circuit components as digital components, and verifying connections using EDA tools to generate a coverage report, facilitating formal proof and reducing verification time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional simulation is used to verify mixed-signal integration, then verification comprehensiveness is improved, but verification time increases excessively
Solution Approach 1:
The verification process is segmented into formal verification (for integration correctness) and simulation verification (for functional validation). Formal verification uses property files to mathematically prove integration correctness without exhaustive simulation, while simulation focuses only on critical functional paths. This segmentation allows comprehensive verification coverage to be achieved with significantly reduced time by applying the appropriate verification method to each segment.
Solution Approach 2:
An executable specification file and formal properties file are introduced as intermediaries between the design netlist and the verification process. These intermediate files capture the integration intent and connections in a formalizable format, enabling automated formal verification tools to efficiently verify integration correctness without requiring time-consuming conventional simulation of the entire mixed-signal design.
2Productivity
If the scope of verification is reduced to decrease verification time, then verification speed is improved, but the risk of approving incorrect designs increases
Solution Approach 1:
Different verification methods are applied to different parts of the design based on local requirements. Formal verification with property files is applied to integration connections and control logic where mathematical precision is critical, while simulation is applied to analog functional behavior where continuous modeling is appropriate. This local quality approach ensures that each verification method is used where it provides the highest reliability, maintaining design correctness while improving overall verification speed.
Data Source
AI summary
Disclosed examples include methods for verifying mixed-signal circuit design, in which an executable specification file is generated including integration abstractions that represent an intended integration of ports and digital circuit blocks of the mixed-signal design, a formal properties file is automatically generated from the executable specification file, an analog circuit component of the mixed-signal circuit design is modeled as a digital circuit component in a model file, at least one analog circuit block of the mixed-signal circuit design is modeled as one or more ports in the model file, and correspondence of connections of the formal properties file and the model file is verified with the mixed-signal circuit design to generate a coverage report file.