Mixed-Signal MAC Array Using Bit-Partitioned Charge Accumulation
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Solution Overview
Problem
Deep Neural Networks (DNNs) face challenges in energy efficiency and performance due to high Analog-to-Digital (A/D) conversion overhead in mixed-signal circuitry, limited information encoding range, and susceptibility to noise, especially in analog operations.
Innovation Solution
The proposed solution involves rearchitecting vector dot-product operations as a series of wide, interleaved, and bit-partitioned arithmetic operations, using mixed-signal units with digital-to-analog converters and capacitors to perform multiplication and accumulation in the analog domain, reducing the need for frequent A/D conversions and leveraging switched-capacitor circuitry for charge-domain operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If mixed-signal circuitry is used to accelerate DNN operations, then performance and energy efficiency are improved, but A/D conversion overhead increases and noise susceptibility worsens
Solution Approach 1:
The input vectors are partitioned into multiple segments of bits, with each segment processed by separate mixed-signal units. This segmentation allows parallel processing while reducing the conversion overhead per unit by distributing the workload across multiple smaller units rather than one large converter.
Solution Approach 2:
The patent transitions from traditional digital-domain processing to mixed-signal domain by introducing analog-to-digital conversion at strategic points only. By performing multiply-accumulate operations in the analog domain and converting only final results, the system adds a dimensional shift from purely digital to hybrid analog-digital processing.
2Productivity
If more mixed-signal compute units are deployed to increase performance, then processing capacity improves, but device complexity and noise susceptibility increase
Solution Approach 1:
Multiple mixed-signal compute units are merged into a unified array architecture where they share common resources including digital-to-analog converters, capacitors for accumulation, and control circuitry. This merging reduces overall device complexity compared to having fully independent units while maintaining high processing capacity through parallel operation.
Solution Approach 2:
The mixed-signal units are designed as universal building blocks that can handle various DNN operations including multiply-accumulate, bit-partitioning, and interleaved arithmetic. Each unit serves multiple functions within the neural network processing pipeline, reducing the need for specialized circuitry for different operation types.
3Loss of energy
If bit-partitioned arithmetic operations are used to reduce A/D conversion overhead, then energy efficiency improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs low-precision analog components such as simple capacitors and resistors that are inexpensive to manufacture and do not require high precision. These components perform computations in the analog domain and are replaced or reconfigured for different operations, sacrificing individual component precision for overall system energy efficiency and reduced manufacturing complexity.
Solution Approach 2:
The system changes the precision parameter dynamically by performing computations in the analog domain where absolute precision is less critical than in digital domain. Bit-partitioning allows the system to work with lower-precision analog representations that can be accumulated and converted back to digital with sufficient accuracy for neural network operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces energy consumption and increases performance by minimizing A/D conversion overhead, enhancing noise robustness, and allowing for a larger number of mixed-signal compute units, achieving 4.5 times the performance of a leading digital accelerator with minimal accuracy loss.
Implementation Method 1
a capacitor coupled to the first digital-to-analog convertor and the second digital-to-analog convertor configured to accumulate a result of the multiplication operation as an analog signal
Implementation Method 2
a first digital-to-analog convertor configured to convert a subset of digital-domain bits partitioned from a first input vector to a first analog-domain signal
Data Source
AI summary
Disclosed are devices, systems and methods for accelerating vector-based computation. In one example aspect, an accelerator apparatus includes a plurality of mixed-signal units, each of which includes a first digital-to-analog convertor configured to convert a subset of digital-domain bits to a first analog-domain signal and a second digital-to-analog convertor configured to convert a subset of digital-domain bits to a second analog-domain signal. Each mixed-signal unit also includes a capacitor coupled to the digital-to-analog convertors to accumulate a result of a multiplication operation as an analog signal. The apparatus includes a circuitry coupled to the mixed-signal units to shift part of the analog signals of the plurality of mixed-signal units. The circuitry comprises an additional capacitor to store an analog-domain result for a multiply-accumulate operation. The apparatus also includes an analog-to-digital converter coupled to the circuitry to convert the analog-domain result into a digital-domain result.