Mixed-Signal Integer Matrix Multiplication With Popcount Reduction
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Solution Overview
Problem
Digital implementations of integer matrix multiplication are inefficient in terms of power consumption and device area, despite their use in various workloads like deep neural networks, where matrix multiplication represents a significant portion of computations.
Innovation Solution
The implementation of integer matrix multiplication using mixed signal circuits, which convert a dot product of vectors into one-bit multiplications and utilize analog and digital domains to optimize energy efficiency, with a mixed-signal Wallace tree reduction and charge-sharing pop counters, achieving improved energy efficiency and reduced device area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If digital implementations are used for integer matrix multiplication, then computational accuracy is maintained, but power consumption and device area increase substantially
Solution Approach 1:
The patent segments the multiplication process into bit-level operations and uses population counting to group identical bit patterns. By dividing the computation into smaller units (individual bit multiplications) and then aggregating results through population counting, the system reduces the number of full-adder operations required, thereby lowering power consumption while maintaining accuracy.
Solution Approach 2:
The patent changes the computational parameters by representing multi-bit numbers as sequences of bit-level operations rather than direct multi-bit arithmetic. This parameter transformation allows the use of population counting techniques that are more energy-efficient than traditional digital adders, achieving lower power consumption without sacrificing computational precision.
2Measurement precision
If digital implementations are used for integer matrix multiplication, then computational accuracy is maintained, but device area increases substantially
Solution Approach 1:
The patent segments the multiplication process into bit-level operations and uses population counting to group identical bit patterns. By dividing the computation into smaller units (individual bit multiplications) and then aggregating results through population counting, the system reduces the number of full-adder operations required, thereby reducing device area while maintaining accuracy.
Solution Approach 2:
The patent uses population counting to copy and aggregate identical bit pattern results across multiple bit positions. Instead of performing separate addition operations for each bit position, the system copies the multiplication results and counts the population of set bits, significantly reducing the number of adders needed and thus reducing device area.
3Productivity
If conventional digital Wallace tree is used, then reduction layers are achieved with O(log n) complexity, but power consumption remains high
Solution Approach 1:
The patent replaces the mechanical adder-based reduction mechanism of the Wallace tree with a population counting approach. Instead of using multiple stages of full-adders and half-adders to reduce partial products, the system uses population counters that exploit the regularity of bit patterns, achieving similar reduction efficiency with lower power consumption.
Solution Approach 2:
The patent changes the reduction mechanism from arithmetic addition to population counting. By transforming the reduction operation from adding multi-bit numbers to counting the number of set bits in binary representations, the system achieves O(log n) reduction complexity while significantly reducing power consumption through more efficient circuit implementation.
Data Source
AI summary
A multiply-accumulate device comprises a digital multiplication circuit and a mixed signal adder. The digital multiplication circuit is configured to input L m1-bit multipliers and L m2-bit multiplicands and configured to generate N one-bit multiplication outputs, each one-bit multiplication output corresponding to a result of a multiplication of one bit of one of the L m1-bit multipliers and one bit of one of the L m2-bit multiplicands. The mixed signal adder comprises one or more stages, at least one stage configured to input the N one-bit multiplication outputs, each stage comprising one or more inner product summation circuits; and a digital reduction stage coupled to an output of a last stage of the one or more stages and configured to generate an output of the multiply-accumulate device based on the L m1-bit multipliers and the L m2-bit multiplicands.