Mixed-Signal Circuit Design Power Data Handling
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Solution Overview
Problem
Standardized power formats for electronic design automation, such as CPF and UPF, are limited in handling non-logic signals and expressions, making it challenging to implement mixed-signal electronic circuit designs effectively.
Innovation Solution
The method involves directly using standardized power data within native processes of these frameworks to evaluate both legal and illegal signals and expressions, without requiring wrappers or translators, allowing for the integration of mixed-signal designs without disrupting the original hierarchical structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If standardized power formats (CPF/UPF) are used to specify power data, then power management and power intent specification are improved, but the ability to handle non-logic signals in mixed-signal designs deteriorates
Solution Approach 1:
The patent introduces an intermediary translation layer that converts non-logic signals into equivalent logic expressions. This intermediary process allows standardized power formats to indirectly handle non-logic signals by translating them into a form that CPF/UPF can process, thus resolving the incompatibility without modifying the core standardized formats.
Solution Approach 2:
The patent transforms the parameter representation of non-logic signals by converting continuous analog signals into discrete logic-level expressions. This parameter transformation enables the standardized power formats to work with mixed-signal designs by changing the signal representation from analog domain to digital domain equivalents.
2Adaptability or versatility
If wrappers are used to handle non-logic signals, then compatibility with standardized power formats is improved, but design hierarchy structure and complexity are worsened
Solution Approach 1:
The patent extracts the signal translation function from the hierarchical design structure and places it in a separate preprocessing stage. By taking out the translation requirement from within the design hierarchy, the patent avoids adding wrapper layers that would complicate the design structure, while still achieving compatibility with standardized power formats.
Solution Approach 2:
The patent performs signal translation as a preliminary action before the power data specification stage. By converting non-logic signals to logic expressions upfront, the patent eliminates the need for wrappers during subsequent design stages, thereby maintaining design hierarchy simplicity while ensuring format compatibility.
3Adaptability or versatility
If translators are used to convert non-logic signals, then recognition by standardized power formats is improved, but processing overhead and design task complexity are worsened
Solution Approach 1:
The patent merges the signal translation process with the existing power data extraction and specification workflows. By combining multiple functions into unified processing steps, the patent reduces redundant operations and minimizes processing overhead, thereby maintaining design productivity while achieving signal recognition capability.
Solution Approach 2:
The patent implements self-service mechanisms where the EDA tools automatically perform signal translation and recognition without requiring manual intervention. This automation reduces the complexity burden on designers and maintains processing efficiency by eliminating manual translation steps.
Data Source
AI summary
Some aspects are directed at methods and systems that directly specifies or uses standardized power data in standardized format(s) in various design tasks for implementing mixed-signal electronic designs by using native process(es) or module(s) of standardized power format framework(s) to evaluate legal signals or expressions to generate the first output and evaluation process(es) or module(s) to evaluate illegal signals or expressions to generate the second output for the design tasks, without using wrappers to encapsulate circuit blocks generating illegal signals and hence disrupt the original design hierarchical structures or using translators to translate illegal signals or expressions into corresponding legal signals or expressions for the standardized power format frameworks. The methods or systems evaluate combinations of legal and illegal signals and expressions by forwarding both the first and second outputs to standardized power format frameworks to use their native process(es) or module(s) to evaluate the combinations.