Mixed-Signal Test Pattern Generation Using Scan-Based Defect Simulation
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Solution Overview
Problem
Current testing methods for analog and mixed-signal circuits are inefficient and time-consuming, relying on functional testing that requires specialized equipment and complex simulations, with no general method for generating tests for various types of circuit defects.
Innovation Solution
Automatically generating test patterns for structural testing by applying predetermined DC voltage values, using scan-based structural testing with threshold-comparing convertors and node-connecting devices to simulate defects and capture responses, and employing a greedy algorithm to reduce the test pattern set.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If functional testing is used for analog and mixed-signal circuits, then the testing can validate circuit operation according to functional specification, but the test generation and execution time becomes very long and specialized ATE equipment is required
Solution Approach 1:
The patent replaces traditional functional testing mechanisms with a structural testing approach that uses scan chains and digital test patterns. Instead of applying complex functional stimuli and analyzing analog responses with specialized ATE, the invention converts analog circuit testing into a digital-based structural testing problem using scan-based test pattern generation and response capture.
Solution Approach 2:
The patent changes the testing parameters from functional specification-based validation to structural defect detection. By transforming the test objectives from validating functional operation to detecting manufacturing defects through scan chain responses, the testing approach achieves faster execution while maintaining reliability through comprehensive defect coverage.
2Reliability
If specification-based testing is used, then the complete end-to-end function is tested, but the testing process becomes very time-consuming to simulate
Solution Approach 1:
The patent segments the testing process into separate test patterns that can be generated and simulated independently. Instead of simulating complete end-to-end functional scenarios, the invention breaks down testing into discrete scan chain operations with individual test patterns, allowing parallel processing and faster simulation while still achieving comprehensive coverage.
3Measurement precision
If analog defect simulation is performed to determine defect coverage, then defect detection capability is assessed, but each potential defect simulation takes minutes to days
Solution Approach 1:
The patent uses digital copies and models of defect conditions through scan chain responses rather than performing time-consuming analog simulations. By representing defect states as digital patterns in scan chains and using logical analysis to assess defect coverage, the invention achieves precise measurement of defect detection capability without the computational burden of detailed analog simulations.
Data Source
AI summary
A method comprising: applying pre-determined DC voltage values to analog inputs of an analog or mixed signal circuit design (710); applying a plurality of sets of bit values generated for scan-based structural testing of circuits manufactured based on the circuit design, one set during each of a plurality of consecutive time intervals, to inputs of one or more node-connecting devices coupled to or to be coupled to one or more selected internal nodes of the circuit design, to one or more selected digital inputs of the circuit design, or both (720); and performing a simulation of the circuit design to determine, for each set of bit values, expected test response bit values at outputs of one or more threshold-comparing convertors and at selected digital signal nodes if the circuit design has the selected digital signal nodes (730). These operations may be repeated on the circuit design with defects being injected.