Mixed-Signal Dot Product Circuit With Shared Capacitor Switching
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Solution Overview
Problem
Emerging sensor-rich and computing platforms require efficient analog and digital mixed-signal processing to avoid the high costs of Analog-to-Digital Conversion (ADC) while performing key machine learning operations like dot product computations.
Innovation Solution
A mixed-signal dot product processor with a single capacitor per multiplier, utilizing a plurality of mixed-signal multiplier branches with dedicated and shared capacitors, and switch configurations to enable various modes of operation, reducing the need for multiple capacitors and minimizing energy consumption and area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple capacitors are used per multiplier in mixed-signal processing, then computation accuracy is improved, but area and energy consumption increase
Solution Approach 1:
The patent merges the functions of multiple capacitors into a single shared capacitor by time-multiplexing its usage across multiple multiplier branches. The capacitor is sequentially allocated to different branches during different time slots, allowing one capacitor to serve what would traditionally require multiple capacitors, thereby reducing total capacitor area while maintaining computation accuracy
Solution Approach 2:
The patent introduces dynamic switching control to allocate the single capacitor to different multiplier branches at different times. Through dynamic time-multiplexed switching, the system ensures that each branch receives adequate capacitive resources when needed, maintaining computational precision while utilizing a shared capacitor across multiple branches
2Measurement precision
If multiple capacitors are used per multiplier in mixed-signal processing, then computation accuracy is improved, but energy consumption increases
Solution Approach 1:
The patent combines multiple capacitor instances into a single shared capacitor that is time-multiplexed across multiple multiplier branches. This merging reduces the total number of capacitors from N to 1, directly reducing the energy required for charging and discharging operations while maintaining the necessary computational accuracy through proper timing control
Solution Approach 2:
The patent implements periodic time-multiplexed switching to allocate the shared capacitor to different multiplier branches in sequential time slots. This periodic allocation ensures that each branch receives the capacitor's services in turn, maintaining computation accuracy while reducing total energy consumption compared to having dedicated capacitors for each branch
3Reliability
If dedicated capacitors are allocated to each multiplier branch, then computation reliability is improved, but device complexity increases
Solution Approach 1:
The patent makes a single capacitor universal by enabling it to serve multiple multiplier branches through time-multiplexed switching. The capacitor transitions from being dedicated to a single branch to being a shared resource that can be dynamically allocated to any branch that needs it, reducing device complexity while maintaining reliability through proper resource management
Solution Approach 2:
The patent introduces switching circuitry as an intermediary that manages the shared capacitor's allocation to different multiplier branches. This intermediary control mechanism ensures that the single capacitor is properly timed and routed to the correct branch, maintaining computation reliability while avoiding the need for multiple dedicated capacitors
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for efficient dot product computations with significantly reduced capacitor area and energy consumption, making it suitable for machine learning algorithms and other logic operations, thereby avoiding the high costs associated with ADC usage.
Implementation Method 1
a first capacitor in series with a second capacitor, the first capacitor having a first node, a second node, and a third node, the second capacitor having a fourth node, a fifth node, and a sixth node
Data Source
AI summary
A mixed-signal logic processor is provided. The mixed-signal logic processor includes a plurality of mixed-signal multiplier branches. Each of the plurality of mixed-signal multiplier branches has a set of branch-dedicated switches and a single branch-dedicated capacitor. The mixed-signal logic further includes a common switch. The common switch is external and common to each of the plurality of mixed-signal multiplier branches. The mixed-signal logic also includes a first shared branch-external capacitor and a second shared branch-external capacitor. The first and the second shared branch-external capacitors are external to and shared by each of the plurality of mixed-signal multiplier branches. Various settings of the set of switches and the common switch enable various modes of the mixed-signal dot product processor.