Simulator Interconnect Delay Compensation for Mixed-Signal Timing
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Solution Overview
Problem
Mixed-signal simulators face timing errors during digital-to-analog and analog-to-digital signal conversions, leading to decreased accuracy in modeling due to interconnect delays, which existing technologies fail to adequately compensate for.
Innovation Solution
A method that generates rising and falling times and adjusts interconnect delay descriptions in SDF files using a netlist and SPEF files to synchronize digital and analog signals, employing equations like A=C−B/2 to compensate for delays, and uses these adjustments to generate events and analog signals that reflect the corrected delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If interconnect delay is not compensated in SDF files during digital-to-analog and analog-to-digital signal conversion, then the simulation process is simple and fast, but timing errors occur and modeling accuracy decreases
Solution Approach 1:
The patent applies preliminary action by pre-calculating and compensating for interconnect delays in the SDF file before simulation begins. The delay compensation value is computed in advance based on the difference between actual and standard delay models, then applied to adjust event timing in the digital domain. This eliminates timing errors during D/A and A/D conversions without adding runtime complexity to the simulation process.
2Reliability
If standard delay format files are used without adjustment, then the simulation setup is straightforward, but timing synchronization errors occur between digital and analog domains
Solution Approach 1:
The patent changes the delay parameter in the SDF file by computing a compensation value that adjusts the interconnect delay description. This parameter modification ensures that digital events are timed correctly relative to analog signals during conversion processes. The adjusted delay parameter maintains setup simplicity while achieving reliable timing synchronization between domains.
3Loss of time
If interconnect delay compensation is implemented using rising and falling time calculations, then timing accuracy improves, but the computational process becomes more complex
Solution Approach 1:
The patent extracts only the essential delay compensation calculation from the full simulation process. By focusing specifically on adjusting the interconnect delay parameter in the SDF file based on rising and falling time differences, it isolates the critical timing correction mechanism. This extraction approach reduces timing errors without requiring complex modifications to the overall simulation architecture.
Data Source
AI summary
A simulator includes a memory for storing a first netlist, a timing library, and a standard parasitic exchange format (SPEF) file; and a processor configured to compensate for delay to synchronize digital and analog signals. The processor includes a delay calculator module for generating one of a rising time and a falling time and a standard delay format (SDF) file using the first netlist, the timing library, and the SPEF file; an SDF file converter module for adjusting an interconnect delay description included in the SDF file to compensate for delay using the one of the rising time and the falling time; and a digital simulator module for generating an event using a first driving cell according to a compensated interconnect delay description.