Mixed Signal Testing Parallel Computation Overlap
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Solution Overview
Problem
The cost of testing semiconductor devices, particularly mixed signal devices, is high due to the time-consuming nature of Fast Fourier Transforms (FFT) and other computations involved in the testing process, which becomes even more prominent during multi-site testing.
Innovation Solution
A system and method for testing semiconductor devices that utilize overlapping test setups, where various test system elements are configured and prepared concurrently with test execution, and software computation modules process data in parallel, sharing results through shared information storage, thereby separating complex computations and data compilation from test execution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Fast Fourier Transforms and other computations are performed during mixed signal testing, then testing accuracy and reliability are improved, but testing time increases exponentially
Solution Approach 1:
The system performs computations such as Fast Fourier Transforms in advance during test setup and configuration phases, before actual device testing begins. By pre-processing and pre-computing algorithms during overlapping test setups, the system eliminates the need to perform these time-consuming computations during the actual test execution, thus maintaining reliability while significantly reducing testing time.
Solution Approach 2:
The testing process is divided into separate overlapping phases: test setup phase, test execution phase, and data analysis phase. Each phase can be worked on independently and concurrently with other phases. Computations are segmented and performed during setup phases while tests are executing, rather than sequentially during test execution, thereby resolving the time-accuracy tradeoff.
2Productivity
If multi-site testing is performed on mixed signal devices, then testing throughput is improved, but time delay increases prominently
Solution Approach 1:
For multi-site testing, the system performs preliminary configuration and computation setup for multiple test sites concurrently during overlapping phases. Test setups for multiple sites are prepared in advance with pre-computed parameters, allowing parallel test execution without sequential delays. This preliminary preparation eliminates the prominent time delays that would otherwise occur during multi-site testing operations.
Solution Approach 2:
The system maintains continuous useful action by implementing overlapping test setups where computation, configuration, and execution phases occur concurrently across multiple sites. While one site is executing tests, other sites are performing setup and computation, ensuring that productive work is continuously happening across all sites without idle time delays.
3Measurement precision
If complex computations and data compilation are performed during test execution, then test result accuracy is improved, but test execution speed decreases
Solution Approach 1:
The system segments the testing process into distinct phases: fast test execution phase that collects raw data, and separate data compilation phase that performs complex computations. Test execution speed is maximized by performing only simple data acquisition during the execution phase, while complex computations are deferred to the compilation phase using pre-prepared algorithms and overlapping setup procedures, thus maintaining both speed and accuracy.
Solution Approach 2:
Complex computation algorithms and data processing procedures are prepared in advance during test setup phases. By pre-configuring analysis parameters, pre-computing transformation algorithms, and preparing data structures before test execution, the system enables rapid test execution followed by efficient data compilation, rather than performing all computations during execution which would slow down the process.
Data Source
AI summary
The present application describes a system and method for testing semiconductor devices and specifically for testing mixed signal semiconductor devices. The test systems are configured to test the semiconductor devices using overlapping test setups by configuring various test system elements. The various test system elements are programmed and prepared for subsequent tests concurrently with tests executing on the semiconductor devices. The test results are computed by various software computation modules configured to independently execute in parallel with the subsequent tests. The resultant test data of an executed test is shared among the various concurrently executing software computation modules using shared information storage. A tester user interface, executing on test system, provides an interface between user test scripts and software computation modules. Therefore, separating complex computations and data compilation from test execution in the test system results in significantly faster and efficient semiconductor device testing.