Mixed-Size Latency Buffer Allocation for Image Compositing

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Solution Overview

Problem

Existing image processing apparatuses face challenges in efficiently managing latency buffers to prevent buffer underrun and reduce memory transactions, particularly due to high resolution requirements and the need for timely availability of image data for compositing multiple layers.

Innovation Solution

The use of mixed-sized latency buffers, where at least one buffer is larger than the others, allows for earlier availability of image data for significant layers, enabling efficient allocation based on characteristics like opacity and geometric processing, thereby reducing unnecessary processing and memory transactions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If all latency buffers are increased in size to ensure timely availability of all image data, then buffer underrun is prevented, but memory resource usage and device complexity increase

Engineering Contradiction:
Improvebuffer underrun preventionVSAvoidbuffer size configuration
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The latency buffer is segmented into multiple buffers, each dedicated to storing image data for a specific layer. This segmentation allows each buffer to be optimized independently based on the characteristics and timing requirements of its associated layer, preventing the need for a single large buffer that would increase overall complexity and resource usage.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Each latency buffer is configured with a size appropriate for its specific layer's requirements rather than using a uniform size for all buffers. This local optimization ensures that critical layers with tight timing requirements have sufficient buffering capacity, while less critical layers use smaller buffers, thereby preventing buffer underrun without unnecessarily increasing overall device complexity.

Inventive Principle:
Principle #3Local quality

2Productivity

If latency buffers are made larger to store more image data, then processing efficiency is improved, but memory resource consumption increases

Engineering Contradiction:
Improveprocessing efficiencyVSAvoidmemory resource usage
Core Design Contradiction:
ProductivityVSQuantity of substance

Solution Approach 1:

The system dynamically allocates buffer sizes based on the characteristics and timing requirements of each layer. This dynamic configuration allows the memory resources to be adaptively distributed, ensuring that layers requiring higher processing priority or having stricter timing constraints receive larger buffers, while other layers use smaller buffers, thereby maintaining high processing efficiency without excessive memory resource consumption.

Inventive Principle:
Principle #15Dynamics

3Speed

If image data is made available earlier for all layers, then compositing speed is improved, but unnecessary processing and memory transactions increase

Engineering Contradiction:
Improvecompositing speedVSAvoidunnecessary processing
Core Design Contradiction:
SpeedVSLoss of energy

Solution Approach 1:

Image data for each layer is made available in advance in its dedicated latency buffer at the appropriate time for compositing. This preliminary action ensures that data is ready when needed without requiring premature retrieval from memory, thereby improving compositing speed while avoiding unnecessary processing and memory transactions that would occur if all layers were prepared simultaneously regardless of their actual timing requirements.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS9805478B2Compositing plural layer of image data for display
Publication Date: 2017.10.31 ARM LTD
  • US9805478B2 patent drawing
  • US9805478B2 patent drawing
  • US9805478B2 patent drawing

AI summary

Apparatus and a corresponding method for processing image data are provided. The apparatus has compositing circuitry to generate a composite layer for a frame for display from image data representing plural layers of content within the frame. Plural latency buffers are provided to store at least a portion of the image data representing the plural layers. At least one of the plural latency buffers is larger than at least one other of the plural latency buffers. The compositing circuitry is responsive to at least one characteristic of the plural layers of content to allocate the plural layers to respective latency buffers of the plural latency buffers. Image data information for a layer allocated to the larger latency buffer is available for analysis earlier than that of the layers allocated to the smaller latency buffers and processing efficiencies can then result.