Mixed-Size PIM Cores for Near-Memory Processing Efficiency
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Solution Overview
Problem
In near-memory processing (NMP) environments, existing systems face inefficiencies due to the inability to correctly separate code for execution between host cores and Processing-In-Memory (PIM) cores, leading to suboptimal performance as computationally intensive tasks may not benefit from parallel execution on small PIM cores and consume bandwidth when returned to host cores.
Innovation Solution
Implementing a computing environment with a mix of large and small PIM cores, where large cores handle sequential compute-bound tasks and small cores handle parallel bandwidth-bound tasks, optimizing data transfer and processing efficiency by subdividing the substrate for different core types and powering them down when idle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If all PIM cores are made equal in size, then the device complexity is reduced and manufacturing is easier, but the processing efficiency deteriorates because computationally intensive tasks cannot be optimized on sequential cores while parallel tasks cannot be optimized on multiple cores
Solution Approach 1:
The PIM core population is segmented into two distinct groups: large PIM cores for sequential compute-bound tasks and small PIM cores for parallel bandwidth-bound tasks. This segmentation allows each core type to be optimized for its specific workload, resolving the contradiction between processing efficiency and device complexity by organizing complexity into functional categories rather than uniform structures.
Solution Approach 2:
Different regions of the PIM array are assigned different core sizes based on local task requirements. Large cores are deployed where sequential computation is needed, while small cores are deployed where parallel processing is beneficial. This local differentiation of core quality enables optimized processing efficiency without requiring complete redesign of the entire PIM system.
2Productivity
If computationally intensive tasks are returned to host cores for execution, then the processing efficiency improves, but the bandwidth consumption increases and the loss of time increases due to data transfer delays
Solution Approach 1:
Computationally intensive sequential tasks are extracted from the host core and executed directly on large PIM cores within the memory array. This extraction eliminates the need to return tasks to host cores, thereby reducing bandwidth consumption and avoiding data transfer delays while maintaining high processing efficiency through in-memory execution.
3Productivity
If small PIM cores are used for all tasks, then the device complexity is reduced and manufacturing is easier, but the processing efficiency deteriorates because computationally intensive sequential tasks cannot be executed effectively
Solution Approach 1:
The PIM core population is segmented into large and small cores with distinct functional roles. Large cores handle sequential compute-bound tasks that require significant processing power, while small cores handle parallel bandwidth-bound tasks. This segmentation resolves the contradiction by allowing small cores to be used for suitable tasks (maintaining simplicity) while introducing large cores only where needed (improving efficiency).
Data Source
AI summary
A device is configured to be in communication with one or more host cores via a first communication path. A first set of processing-in-memory (PIM) cores and a second set of PIM cores are configured to be in communication with a memory included in the device over a second communication path, wherein the first set of PIM cores have greater processing power than the second set of PIM cores, and wherein the second communication path has a greater bandwidth for data transfer than the first communication path. Code offloaded by the one or more host cores are executed in the first set of PIM cores and the second set of PIM cores.