Mixed SOI-Bulk MOSFET Structure for Leakage Isolation
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Solution Overview
Problem
The semiconductor industry faces challenges in implementing silicon-on-insulator (SOI) technology due to the complex circuit design requirements and differences in device behavior compared to bulk silicon substrates, necessitating improved processing and manufacturing methods for producing high-performance semiconductor chips with varying regions of speed and power.
Innovation Solution
A semiconductor device structure and manufacturing method involving a SOI structure with a patterned mask layer, shallow trench isolation, and epitaxial growth of a bulk semiconductor layer, allowing for the formation of MOSFET devices on both SOI and bulk silicon regions with different active silicon layer thicknesses for varied device characteristics, and dielectric spacer layers for full dielectric isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If SOI technology is implemented to achieve higher speed performance and reduced power consumption, then device performance is improved, but circuit design complexity increases due to different device behavior compared to bulk silicon
Solution Approach 1:
The substrate is divided into multiple regions with different semiconductor layer configurations: a first region with a first thickness and a second region with a second thickness. This segmentation allows different circuit regions to have optimized device characteristics for their specific functions, improving overall performance while providing design flexibility to manage complexity.
Solution Approach 2:
Different regions of the substrate are assigned different semiconductor layer thicknesses to create locally optimized device properties. The first region has a first thickness tailored for specific performance requirements, while the second region has a second thickness optimized for different requirements, allowing each region to have the quality needed for its specific function.
2Ease of manufacture
If uniform semiconductor layer thickness is used across the substrate, then manufacturing process is simpler, but device characteristics cannot be varied to optimize different circuit regions for speed and power
Solution Approach 1:
The manufacturing process segments the substrate into multiple regions during the epitaxial growth stage, forming different semiconductor layer thicknesses in different regions. This approach maintains manufacturing simplicity by using a single continuous process while achieving the versatility of varied device characteristics across different circuit regions.
Solution Approach 2:
The manufacturing process creates local quality variations by forming a first semiconductor layer with a first thickness in a first region and a second semiconductor layer with a second thickness in a second region. This allows device characteristics to be optimized for different circuit regions while using a unified manufacturing approach.
3Strength
If thicker semiconductor layer is used, then device robustness is improved, but electrostatic control deteriorates leading to increased current leakage
Solution Approach 1:
Different regions are assigned different semiconductor layer thicknesses to balance robustness and electrostatic control. Regions requiring high robustness have thicker layers, while regions requiring superior electrostatic control have thinner layers. This local optimization allows each region to have the thickness appropriate for its specific functional requirements.
Solution Approach 2:
The solution moves from a single-dimensional thickness parameter to a two-dimensional thickness map across the substrate. By varying thickness in the spatial dimension, the patent simultaneously achieves robustness in some regions and electrostatic control in others, resolving the contradiction through dimensional expansion of the design space.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the production of semiconductor devices with improved performance and reduced power consumption by allowing for distinct device characteristics on the same substrate, enhancing electrostatic control and minimizing current leakage, thereby addressing the complexity of SOI technology integration.
Implementation Method 1
an insulator layer disposed between and in contact with the semiconductor substrate and the semiconductor layer
Implementation Method 2
a spacer layer on the semiconductor substrate, the spacer layer isolating the first MOSFET device from the second MOSFET device
Data Source
AI summary
A semiconductor device structure includes a first MOSFET device disposed at a first region of a semiconductor substrate, the first MOSFET device comprises a bulk semiconductor layer contacting the semiconductor substrate, and the bulk semiconductor layer has a first height, a first gate structure over the bulk semiconductor layer, and first S/D regions disposed in the bulk semiconductor layer on opposite sides of the first gate structure; a second MOSFET device disposed at a second region of the semiconductor substrate, the second MOSFET device comprises a semiconductor layer over the semiconductor substrate, and the semiconductor layer has a second height different than the first height, a second gate structure over the semiconductor layer, and second S/D regions disposed in the semiconductor layer on opposite sides of the second gate structure; an insulator disposed between and in contact with the semiconductor substrate and semiconductor layer; and a spacer layer isolating first and second MOSFET devices, and a portion of the spacer layer is disposed between and in contact with the insulator layer and bulk semiconductor layer.