Multi-Plane Mixed Sub-Block Programming in Non-Volatile Memory
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Solution Overview
Problem
Current semiconductor memory systems face inefficiencies in programming data due to sequential operation of memory cells, which slows down the process and reduces performance, especially when dealing with large memory capacities.
Innovation Solution
Implementing a memory system architecture that allows simultaneous programming of memory cells across different word lines in various sub-blocks and planes of a die, utilizing a control circuit to manage independent erasure, reading, and programming of sub-blocks, and applying distinct programming voltages and bit line signals to optimize performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If sequential programming of memory cells is used, then device complexity is reduced, but programming speed and productivity deteriorate
Solution Approach 1:
The memory system is divided into multiple independent planes, with each plane containing multiple blocks and sub-blocks that can be programmed independently. This segmentation enables parallel programming operations across different planes, significantly improving programming speed without requiring complex inter-plane coordination circuits.
Solution Approach 2:
The patent introduces a multi-plane dimensional structure where memory cells are organized across multiple planes stacked vertically. This spatial dimensionality change allows simultaneous programming operations in different planes, transforming the sequential single-plane programming into parallel multi-plane programming, thereby improving productivity without proportionally increasing device complexity.
2Productivity
If simultaneous programming across multiple planes is implemented, then programming efficiency improves, but control circuit complexity increases
Solution Approach 1:
The control circuit is segmented into plane-specific control units, where each plane has its own dedicated control logic for programming operations. This segmentation allows independent control of each plane, simplifying the overall control architecture while enabling parallel programming across multiple planes, thus improving efficiency without requiring a monolithic complex control circuit.
Solution Approach 2:
The control circuit receives programming data in advance and performs preliminary processing and buffering before actual programming operations. This preliminary action allows the control circuit to prepare control signals for multiple planes simultaneously, reducing the real-time control complexity while maintaining high programming efficiency through pre-coordinated parallel operations.
Data Source
AI summary
A non-volatile memory system includes a control circuit connected to non-volatile memory cells. The control circuit is configured to simultaneously program memory cells connected to different word lines that are in different sub-blocks of different blocks in different planes of a die.