Mixed TFT Substrate for Low Power Displays

The patent segments the transistor population into two distinct types: low-power transistors for switching elements and high-speed transistors for driver elements. This segmentation allows each transistor type to be optimized for its specific function, reducing overall power consumption while maintaining display performance through differentiated transistor characteristics.

The patent applies local quality by assigning different transistor types to different functional regions within the display device. Switching elements use low-power transistors optimized for power efficiency, while driver elements use high-speed transistors optimized for performance. This localized optimization resolves the contradiction by tailoring transistor properties to specific functional requirements.

The manufacturing process is segmented into common steps applicable to all transistors and differentiated steps for specific transistor types. Common steps include substrate preparation and base layer formation, while differentiated steps include selective material deposition and processing parameters. This segmented approach maintains manufacturing simplicity while enabling power consumption optimization through transistor type differentiation.

The patent employs universal manufacturing processes that can produce multiple transistor types from the same production line. By using compatible materials and processes that accommodate both low-power and high-speed transistor requirements, the manufacturing system maintains simplicity and flexibility while producing differentiated transistor types for optimal power consumption.

The patent applies local quality by strategically placing high-speed transistors only where performance is critical (driver elements) and using low-power transistors elsewhere (switching elements). This localized high-performance approach maintains display performance in critical regions while minimizing overall power consumption through selective transistor type deployment.

Instead of the conventional approach of using high-performance transistors throughout, the patent inverts the strategy by using low-power transistors as the default and selectively deploying high-speed transistors only where necessary. This inverted approach prioritizes power consumption reduction while maintaining performance through targeted high-speed transistor placement.