Mixed-Threshold Memory Macro for Sub-65nm Density and Retention
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Solution Overview
Problem
Conventional embedded DRAM technologies, such as 2T bitcells, face challenges in deeply-scaled CMOS nodes below 65 nm due to reduced parasitic storage capacitances and increased leakage currents, leading to shorter data retention times and higher power consumption.
Innovation Solution
The implementation of a high-density memory macro using an array of mixed threshold 4T bitcells with low threshold voltage (LVT) transistors and level-shifting write drivers, along with high-speed differential sense amplifiers and configurable reference voltages, enhances read and write operations, reducing propagation delay and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional 2T bitcells are used in sub-65 nm technology nodes, then device density is improved, but data retention time deteriorates due to reduced parasitic storage capacitances and increased leakage currents
Solution Approach 1:
The patent applies local quality by using low threshold voltage (LVT) transistors specifically for read operations and regular threshold voltage (RVT) transistors for write and storage operations. This local differentiation allows the read transistor to operate faster while the storage transistor maintains better retention characteristics, resolving the contradiction between speed and retention in scaled technologies.
Solution Approach 2:
The patent changes the threshold voltage parameter of transistors based on their functional role. LVT transistors are used where fast switching is needed (read operations), while RVT transistors are used where stability is needed (storage and write operations). This parameter optimization allows the circuit to maintain both high speed and adequate data retention in deeply-scaled nodes.
2Quantity of substance
If conventional 2T bitcells are used in sub-65 nm technology nodes, then device density is improved, but power consumption deteriorates due to increased leakage currents
Solution Approach 1:
The patent applies local quality by using low threshold voltage (LVT) transistors specifically for read operations and regular threshold voltage (RVT) transistors for write and storage operations. This local differentiation allows the read transistor to operate faster while the storage transistor maintains better retention characteristics, resolving the contradiction between speed and retention in scaled technologies.
Solution Approach 2:
The patent changes the threshold voltage parameter of transistors based on their functional role. LVT transistors are used where fast switching is needed (read operations), while RVT transistors are used where stability is needed (storage and write operations). This parameter optimization allows the circuit to maintain both high speed and adequate data retention in deeply-scaled nodes.
3Speed
If high-speed read operations are implemented using LVT transistors, then read speed is improved, but write operation reliability deteriorates due to insufficient voltage margins
Solution Approach 1:
The patent applies local quality by using low threshold voltage (LVT) transistors specifically for read operations and regular threshold voltage (RVT) transistors for write and storage operations. This local differentiation allows the read transistor to operate faster while the storage transistor maintains better retention characteristics, resolving the contradiction between speed and retention in scaled technologies.
Solution Approach 2:
The patent introduces level-shifting write drivers as an intermediary component between the logic circuit and the memory array. These drivers restore and shift the voltage levels of write signals to ensure sufficient voltage margins for reliable write operations, even when LVT transistors are used in the bitcell. This intermediary compensates for the voltage degradation that would otherwise compromise write reliability.
4Device complexity
If conventional write drivers are used, then device complexity is minimized, but write speed deteriorates due to insufficient voltage driving capability
Solution Approach 1:
The patent introduces level-shifting write drivers as an intermediary component between the logic circuit and the memory array. These drivers restore and shift the voltage levels of write signals to ensure sufficient voltage margins for reliable write operations, even when LVT transistors are used in the bitcell. This intermediary compensates for the voltage degradation that would otherwise compromise write reliability.
Solution Approach 2:
The write drivers are designed with dynamic voltage shifting capability, allowing them to adaptively adjust the voltage levels of write signals based on the operating conditions and the specific memory cell being accessed. This dynamic adjustment ensures optimal write speed and reliability across different operating scenarios.
Data Source
AI summary
A high-density memory includes: a data write interface, a data read interface, an array of memory cells and level-shifting write drivers. The data write interface inputs data written to the memory. The data read interface outputs data read from the memory. The array of memory cells stores data input at the data write interface and outputs stored data to the data read interface. Each of the memory cells includes at least one low threshold voltage (LVT) read transistor and at least one respective regular threshold voltage (RVT) transistor, so as to obtain high-speed read operations. The level-shifting write drivers supply shifted write wordline voltages to the array, so as to obtain high-speed write operations.