Mixed-Transistor Timing Analysis via Segmented STA and Simulation
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Solution Overview
Problem
Current high-performance integrated circuit (IC) design faces challenges in accurately analyzing timing violations due to the lack of correlation between different transistor types, leading to inefficiencies in timing closure and increased complexity in mixed-transistor type designs.
Innovation Solution
A method for timing analysis that selects timing paths with mixed transistor types, runs static timing analysis using a delay model that includes cross-terms between global and local variation variables, and determines whether timing requirements are met by simulating different corner conditions for each transistor type, allowing for more accurate timing closure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If static timing analysis with simplified timing models is used, then timing analysis speed is improved, but measurement precision deteriorates
Solution Approach 1:
The patent segments the timing analysis process into two distinct phases: (1) a fast static timing analysis phase using simplified models to identify critical paths, and (2) a rigorous circuit simulation phase applied only to those identified critical paths. This segmentation allows the system to achieve both speed (through STA on all paths) and precision (through simulation on critical paths only), resolving the contradiction between analysis speed and measurement accuracy.
2Measurement precision
If rigorous circuit simulation is used for timing analysis, then measurement precision is improved, but productivity deteriorates
Solution Approach 1:
The patent divides the design cycle into two stages: first, a rapid static timing analysis stage that screens all timing paths to identify critical ones; second, a detailed circuit simulation stage applied only to the identified critical paths. This segmentation enables the design team to maintain high productivity while achieving precise timing measurements on the paths that matter most, rather than performing slow simulations on all paths equally.
Solution Approach 2:
The patent applies partial action by performing rigorous circuit simulation not on all timing paths, but only on the critical subset identified by the initial STA. This partial application of the more accurate (but slower) simulation method achieves the necessary measurement precision for timing closure while avoiding the excessive computational cost of simulating every path, thus maintaining design cycle productivity.
3Adaptability or versatility
If mixed transistor types are used in logic cells, then adaptability is improved, but device complexity increases
Solution Approach 1:
The patent segments the timing analysis process to handle mixed transistor types by first identifying paths containing different transistor types through STA, then applying specialized correlation-aware simulation only to those paths. This segmentation allows the system to maintain design flexibility with mixed transistor types while managing analysis complexity through targeted application of sophisticated models only where needed.
Solution Approach 2:
The patent changes the analysis parameters dynamically based on the transistor type composition of each timing path. For paths with uniform transistor types, standard STA parameters are used. For paths with mixed transistor types, the system switches to correlation-aware simulation parameters that account for the interactions between different transistor types, thus managing complexity through adaptive parameter selection.
Data Source
AI summary
A method for timing analysis includes receiving a physical design of an electric circuit, selecting a timing path within the electric circuit, and determining that the selected timing path includes a first logic cell implemented with a first type of transistor and a second logic cell implemented with a second type of transistor. The method further includes running a set of process corners with the first type of transistor at a given corner and the second type of transistor at a condition other than the given corner. The first type of transistor has a delay that is based on process correlation with the second type of transistor. The method also includes determining whether a timing requirement is met or not met for the selected timing path, and then reporting whether the timing requirement is met or not met.