Threshold Voltage Control for Mixed-Type Non-Planar Devices
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Solution Overview
Problem
Current methods for controlling threshold voltage in semiconductor devices, such as channel doping and work function metal layers, are inadequate for mixed-type non-planar devices, especially as device size decreases and become unstable for p-type devices.
Innovation Solution
A method involving a multi-layer liner with a bottom dielectric layer, p-type work function metal, an etch stop layer, and annealing, followed by the creation of n-type work function metal and filling with conductive material, to achieve different threshold voltages in co-fabricated non-planar semiconductor devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If work function metal layers are used to control threshold voltage, then threshold voltage control is achieved, but stability deteriorates for p-type devices and neighboring devices are affected
Solution Approach 1:
The gate stack is segmented into multiple functional layers: a first work function metal layer for n-type device threshold voltage control, a second work function metal layer for p-type device threshold voltage control, and an intermediate layer separating them. This segmentation allows independent optimization of threshold voltage for each device type without cross-interference, resolving the stability issue while maintaining precise control.
Solution Approach 2:
Different work function metal layers are applied to different regions of the gate stack corresponding to n-type and p-type devices. The first work function metal layer is positioned over n-type device regions while the second work function metal layer is positioned over p-type device regions, ensuring that each device type receives the appropriate work function material for its specific threshold voltage requirements without affecting neighboring devices.
2Productivity
If device size is reduced, then device density and integration are improved, but available space for work function metal decreases and control capability deteriorates
Solution Approach 1:
The solution transitions from horizontal placement of work function metal to a vertical stacked architecture. Multiple work function metal layers are arranged vertically within the gate stack, allowing sufficient work function material to be accommodated in the vertical dimension even as horizontal device dimensions shrink. This maintains threshold voltage control capability while enabling higher device density.
Solution Approach 2:
The gate stack employs a nested structure where multiple work function metal layers are embedded within the vertical gate stack architecture. The first and second work function metal layers are nested between the gate dielectric and the conductive fill, with an intermediate layer separating them. This nested arrangement maximizes the use of vertical space for threshold voltage control without increasing horizontal footprint.
3Ease of manufacture
If channel doping is used to control threshold voltage, then threshold voltage adjustment is convenient, but performance degrades beyond very low doping levels
Solution Approach 1:
The invention replaces the mechanical/chemical process of channel doping with a physical deposition process of work function metal layers. Instead of introducing dopant atoms into the channel region, work function metals are deposited on the gate stack surface. This substitution eliminates the performance degradation associated with doping while maintaining the convenience of threshold voltage adjustment through controlled deposition processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for stable and effective threshold voltage control in mixed-type non-planar semiconductor devices, maintaining performance even as device size shrinks, by using a multi-layer liner and conductive filling to manage voltage levels.
Implementation Method 1
The method further includes annealing the multi-layer liner
Data Source
AI summary
A range of lowest, low and regular threshold voltages are provided to three p-type devices and three n-type devices co-fabricated on a same substrate. For the p-type devices, the range is achieved for the lowest using an additional thick layer of a p-type work function metal in a gate structure and oxidizing it, the low Vt is achieved with the thick p-type work function metal alone, and the regular Vt is achieved with a thinner layer of the p-type work function metal. For the n-type devices, the lowest Vt is achieved by implanting tantalum nitride with arsenic, argon, silicon or germanium and not adding any of the additional p-type work function metal in the gate structure, the low Vt is achieved by not adding the additional p-type work function metal, and the regular Vt is achieved with a thinnest layer of the p-type work function metal.