Mixed Via Configurations for Lower RC Delay in IC Interconnects
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Solution Overview
Problem
As integrated circuit (IC) technologies advance to sub-20 nm technology nodes, shrinking critical dimensions of interconnects leads to increased resistance-capacitance (RC) delay due to poor metal gap filling and contact resistance issues, particularly in vias to source/drain contacts and gate structures, where the metal glue/barrier layer consumption reduces via opening space and increases contact resistance.
Innovation Solution
The proposed solution involves mixing via configurations by including a metal glue/barrier layer for vias to gate structures and eliminating it for vias to source/drain contacts, using a bottom-up deposition process to fill via openings, and performing planarization to optimize contact resistance reduction, while tuning the via rivet head height to minimize internal stress and prevent cracking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a metal glue/barrier layer is included in vias to improve adhesion and prevent diffusion, then reliability is improved, but the via opening space is reduced and contact resistance increases
Solution Approach 1:
The patent applies different via configurations selectively: vias to gate structures include a metal glue/barrier layer for adhesion and diffusion prevention, while vias to source/drain contacts eliminate this layer to reduce contact resistance. This local differentiation resolves the contradiction by optimizing each via type for its specific functional requirements rather than applying a uniform structure.
2Productivity
If geometry size is reduced to increase functional density, then productivity is improved, but RC delay increases due to poor metal gap filling
Solution Approach 1:
The patent changes the structural parameters of vias by eliminating the metal glue/barrier layer in specific via configurations, which improves metal gap filling at reduced geometry sizes. This parameter change allows continued scaling to increase functional density while maintaining lower RC delay by ensuring complete metal fill in the reduced-size via openings.
3Length of stationary object
If via opening size is reduced to achieve smaller geometry, then length is improved, but metal gap filling becomes poor and contact resistance increases
Solution Approach 1:
The patent extracts (eliminates) the metal glue/barrier layer from via structures to improve metal gap filling in reduced-size via openings. By removing this intermediate layer, the via fill process achieves better metal continuity and reduced voids, maintaining manufacturing precision even as via dimensions are reduced for smaller geometry nodes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces capacitance and resistance associated with IC devices, thereby minimizing RC delay and enhancing the performance of scaled-down ICs by improving metal gap filling and contact resistance, leading to more efficient interconnect structures.
Implementation Method 1
forming a via bulk layer in the via opening and overlying the contact, forming a via barrier layer over the via bulk layer, and performing a planarization process that removes portions of the via barrier layer and the via bulk layer that overlie a top surface of the dielectric layer
Data Source
AI summary
Vias, along with methods for fabricating vias, are disclosed that exhibit reduced capacitance and resistance. An exemplary interconnect structure includes a first source/drain contact and a second source/drain contact disposed in a dielectric layer. The first source/drain contact physically contacts a first source/drain feature and the second source/drain contact physically contacts a second source/drain feature. A first via having a first via layer configuration, a second via having a second via layer configuration, and a third via having a third via layer configuration are disposed in the dielectric layer. The first via and the second via extend into and physically contact the first source/drain contact and the second source/drain contact, respectively. A first thickness of the first via and a second thickness of the second via are the same. The third via physically contacts a gate structure, which is disposed between the first source/drain contact and the second source/drain contact.