Mixed-Voltage I/O Buffer with Gate Tracking for Overstress Protection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional mixed-voltage I/O buffers suffer from gate-oxide overstress, hot-carrier degradation, and unpredictable leakage currents when transmitting high-voltage signals, leading to reliability issues in semiconductor devices.
Innovation Solution
A mixed-voltage I/O buffer circuit design incorporating stacked pull-up P-type and pull-down N-type transistors, a dynamic gate bias generator, a gate-tracking circuit, and a floating N-well circuit to prevent leakage currents and duty cycle distortion, along with an input buffer circuit for voltage level limiting and calibration to prevent electrical overstress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a conventional mixed-voltage I/O buffer with one PMOS transistor and one NMOS transistor is used to transmit high-voltage signals (e.g., 5V), then the buffer can interface between different voltage levels, but the output stage circuit suffers from gate-oxide overstress, hot-carrier degradation and unpredictable leakage currents
Solution Approach 1:
The patent divides the output stage into multiple stacked transistors (first PMOS, second PMOS, first NMOS, second NMOS) instead of using single transistors. This segmentation distributes the voltage stress across multiple devices, preventing any single transistor from experiencing gate-oxide overstress when handling high-voltage signals up to 5V.
Solution Approach 2:
The patent introduces intermediate control circuits including a gate-tracking circuit that dynamically adjusts gate voltages and a floating N-well circuit that provides adaptive well biasing. These intermediary circuits act as mediators that protect the output transistors from direct exposure to high voltage stress while maintaining signal transmission capability.
2Reliability
If the output stage uses stacked pull-up P-type transistors and stacked pull-down N-type transistors with dynamic gate bias control, then leakage currents and duty cycle distortion are prevented, but the device complexity increases
Solution Approach 1:
The gate-tracking circuit automatically adjusts the gate voltages of the stacked transistors based on the instantaneous signal conditions without requiring external intervention. The circuit self-regulates to maintain proper voltage levels and minimize leakage currents, reducing the need for complex external control mechanisms.
Solution Approach 2:
The patent combines multiple functions into integrated circuits: the gate-tracking circuit integrates voltage sensing and adjustment functions, while the floating N-well circuit combines well biasing control with transistor protection. This merging reduces overall system complexity compared to using separate discrete control circuits.
Data Source
AI summary
A mixed-voltage I/O buffer includes an input buffer circuit. The input buffer circuit includes a first inverter, a first voltage level limiting circuit, a first voltage level pull-up circuit, an input stage circuit, and a logic calibration circuit. The first inverter inverts an input signal to generate a first control signal. The first voltage level limiting circuit limits voltage level of an external signal to generate the input signal transmitted to the first inverter to prevent electrical overstress of the first inverter. The first voltage level pull-up circuit is controlled by the first control signal to pull up voltage level of the input signal inputted into the first inverter. The input stage circuit receives the first control signal to generate corresponding digital signals inputted into a core circuit. The logic calibration circuit calibrates voltage level of the first control signal when the first inverter mis-operates due to the input signal having a low voltage level.